• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.54-63
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• 2006

This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.6
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• pp.42-48
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• 2002

The design, construction and performance test of a convenient multi-purpose irradiator is described. A multi-purpose irradiator using Cesium-137 has been developed for studies of low dose radiation effects in biology and for calibration of Thermo Luminescent dosimeter(TLD). During the operation, three rods of radioactive material which are 10cm in length revolve 180 degrees and irradiate biological samples, or TLD, and return to their shielded position, after the programmed time. A programmable Logic Controller(PLC) controls the sequence of operation, interlock, motor rotation and safety system. The rotation speed of biological samples can vary up to 20 RPM. A real time monitoring system was also incorporated to check and control the operation status of the irradiator. The capacity of the irradiation chamber was 4.5 liters. The isodose distribution at arbitrary vertical planes was measured by using film dosimetry. The dose-rate was 0.13 cGy/min in air and 0.11 cGy/min in water equivalent material in the case of Cesium-137. Range of activity was 2 Ci. The homogeneity of dose distribution in the chamber was ${\pm}$7%. The actual radiation level on the surface was within permissible levels. The irradiator had a maximum 0.35 mR/min radiation leakage on its surface.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.4 s.310
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• pp.74-86
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• 2006

This paper proposes a robust and computationally efficient algorithm for automatic video object segmentation. For implementing the spatio-temporal segmentation, which aims for efficient combination of the motion segmentation and the color segmentation, an SOM-based hierarchical clustering method in which the segmentation process is regarded as clustering of feature vectors is employed. As results, problems of high computational complexity which required for obtaining exact segmentation results in conventional video object segmentation methods, and the performance degradation due to noise are significantly reduced. A measure of motion vector reliability which employs MRF-based MAP estimation scheme has been introduced to minimize the influence from the motion estimation error. In addition, a noise elimination scheme based on the motion reliability histogram and a clustering validity index for automatically identifying the number of objects in the scene have been applied. A cross projection method for effective object tracking and a dynamic memory to maintain temporal coherency have been introduced as well. A set of experiments has been conducted over several video sequences to evaluate the proposed algorithm, and the efficiency in terms of computational complexity, robustness from noise, and higher segmentation accuracy of the proposed algorithm have been proved.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.1
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• pp.123-132
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• 1999

In this paper, a quadratic sigmoid neural equalizer(QSNE) is proposed to improve the performance of conventional neural equalizer in terms of bit error probability by using a quadratic sigmoid function as the activation function of neural networks. Conventional neural equalizers which have been used to compensate for nonlinear distortions adopt the sigmoid function. In the case of sigmoid neural equalizer, each neuron has one linear decision boundary. So many neurons are required when the neural equalizer has to separate complicated structure. But in case of the proposed QSNF and quadratic sigmoid neural decision feedback equalizer(QSNDFE), each neuron separates decision region with two parallel lines. Therefore, QSNE and QSNDFE have better performance and simpler structure than the conventional neural equalizers in terms of bit error probability. When the proposed QSNDFE is applied to communication systems and digital magnetic recording systems, it is an improvement of approximately 1.5dB~8.3dB in signal to moise ratio(SNR) over the conventional decision feedback equalizer(DEF) and neural decision feedback equalizer(NDFE). As intersymbol interference(ISI) and nonlinear distortions become severer, QSNDFE shows astounding SNR shows astounding SNR performance gain over the conventional equalizers in the same bit error probability.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.5 s.305
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• pp.85-94
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• 2005

Display characterization, deriving the relationship between digital input values and the corresponding CIEXYZ tri-stimulus values, is important to reproduce the accurate color in color management system. The relationship can be estimated from the nine channel TRCs(tone response curves) and the result of this characterization method is better than that of using three channel TRCs. However, the inverse display characterization using nine channel TRCs cannot be directly inverted because the CIEXYZ values corresponding to each of RGB values are inseparable. Accordingly, inverse display characterization is usually implemented by the 3D-LUT (look-up table) method. Although the result of 3B-LUT is accurate, creating the 3D-LUT requires a lot of memory space and considerable amount of measurements. Therefore the inverse characterization method is proposed based on the modeling of channel-dependent values and nine channel inverse process based on the GOG(gain, offset gamma) model. The proposed method enhances the accuracy of display characterization and reduces the complexity and the number of measurements data required for accuracy in 3-D LUT.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.5 s.305
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• pp.123-136
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• 2005

We propose a recognition system for superimposed patterns based on selective attention model and SVM which produces better performance than artificial neural network. The proposed selective attention model includes attention layer prior to SVM which affects SVM's input parameters. It also behaves as selective filter. The philosophy behind selective attention model is to find the stopping criteria to stop training and also defines the confidence measure of the selective attention's outcome. Support vector represents the other surrounding sample vectors. The support vector closest to the initial input vector in consideration is chosen. Minimal euclidean distance between the modified input vector based on selective attention and the chosen support vector defines the stopping criteria. It is difficult to define the confidence measure of selective attention if we apply common selective attention model, A new way of doffing the confidence measure can be set under the constraint that each modified input pixel does not cross over the boundary of original input pixel, thus the range of applicable information get increased. This method uses the following information; the Euclidean distance between an input pattern and modified pattern, the output of SVM, the support vector output of hidden neuron that is the closest to the initial input pattern. For the recognition experiment, 45 different combinations of USPS digit data are used. Better recognition performance is seen when selective attention is applied along with SVM than SVM only. Also, the proposed selective attention shows better performance than common selective attention.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.60-69
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer(PADFE) using a 0.25-${\mu}m$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stages are inserted into the critical path of the ADFE by using delayed least-mean-square(DLMS) algorithm. Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width, and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The single-chip PADFE contains about 205,000 transistors on an area of about $1.96\times1.35-mm^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW. Test results show that the fabricated chip works functionally well.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.59-67
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• 2016

A novel instrumentation amplifier (IA) using fully-differential linear operational transconductance amplifier (FLOTA) for electronic measurement systems with low cost, wideband, and gain control with wide range is designed. The IA consists of a FLOTA, two resistor, and an operational amplifier(op-amp). The principal of the operating is that the difference of two input voltages applied into FLOTA converts into two same difference currents, and then these current drive resistor of (+) terminal and feedback resistor of op-amp to obtain output voltage. To verify operating principal of the IA, we designed the FLOTA and realized the IA used commercial op-amp LF356. Simulation results show that the FLOTA has linearity error of 0.1% and offset current of 2.1uA at input dynamic range ${\pm}3.0V$. The IA had wide gain range from -20dB to 60dB by variation of only one resistor and -3dB frequency for the 60dB was 10MHz. The proposed IA also has merits without matching of external resistor and controllable offset voltage using the other resistor. The power dissipation of the IA is 105mW at supply voltage of ${\pm}5V$.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.12
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• pp.45-51
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• 2010

The main issue in mobile cloud computing is how to support a seamless service to a mobile mode. Mobile IPv6 (MIPv6) is a mobility supporting protocol which is standardized by the Internet Engineering Task Force (IETF). Mobile IPv6 fast handovers (FMIPv6) is the extension of MIPv6 which is proposed to overcome shortcomings of MIPv6. Recently, fast handovers for Mobile IPv6 over IEEE 802.16e which is one of broadband wireless access systems has been proposed by the IETF. It was designed for supporting cross-layer fast handover. In this paper, we propose an enhanced cross-layering mobile IPv6 fast handover over IEEE 802.16e networks. In our scheme, a new access router generates a new address for the mobile node by using a layer 2 trigger. We utilize a layer 2 message which is sent from a new base station to the new access router in order to inform the new access router of information of the mobile node. A previous access router sends a binding update message to the mobile node's home agent when it acquires the new address of the mobile node. We evaluate the performance of the proposed scheme compared with the existing schemes in terms of the signaling cost and the handover latency. From the results, we observe that the proposed scheme can support fast handover effectively over IEEE 802.16e networks than existing schemes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.56-63
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• 2010

This work proposes a 12b 100MS/s 0.13um CMOS pipeline ADC for battery-powered mobile video applications such as DVB-Handheld (DVB-H), DVB-Terrestrial (DVB-T), Satellite DMB (SDMB), and Terrestrial DMB (TDMB) requiring high resolution, low power, and small size at high speed. The proposed ADC employs a three-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. A single shared and switched op-amp for two MDACs removes a memory effect and a switching time delay, resulting in a fast signal settling. A two-step reference selection scheme for the last-stage 6b FLASH ADC reduces power consumption and chip area by 50%. The prototype ADC in a 0.13um 1P7M CMOS technology demonstrates a measured DNL and INL within 0.40LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 60.0dB and a maximum SFDR of 72.4dB at 100MS/s, respectively. The ADC with an active die area of 0.92 $mm^2$ consumes 24mW at 1.0V and 100MS/s. The FOM, power/($f_s{\times}2^{ENOB}$), of 0.29pJ/conv. is the lowest of ever reported 12b 100MS/s ADCs.