• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.687-689
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• 1999

본 논문에서는 이산 제어 시스템의 작업 수행 시, 특정작업에 있어서의 불규칙한 시간 지연 때문에 시스템이 불안정해지는 것을 막기 위해 시간 지연을 갖는 시스템의 안정도를 분석한다. Soft real time OS인 Windows NT 운영체제를 갖는 PC-based 이산 제어 시스템에서는 하드웨어적으로 인터럽트를 사용하여 시간 제한성이 있는 작업을 수행한다. 그러나 인터럽트와 함께 수반되는 DPC(Deferred Procedure Call)의 불규칙한 수행 시간 때문에 다른 작업이 수행되어야 할 표본시간이 길어지게 된다. 이러한 현상으로 다른 작업의 시간 지연이 발생하게 되며, 시간 지연은 시스템을 불안정하게 하는 요인이 된다. 안정성 분석 면에서 보면, 시간 지연을 고려하지 않은 시스템의 극점은 안정한 위치에 존재하게 되는데 반해, 시간 지연을 고려한 시스템의 극점은 불안정한 위치에 존재하게 된다. 따라서 본 논문에서는 시간 지연이 존재하는 제어 시스템의 안정성을 보장하기 위해서 시스템의 안정성을 분석한다.

• Journal of Advanced Marine Engineering and Technology
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• v.33 no.5
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• pp.721-728
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• 2009

PID control is widely used to control stable processes, however, PID control for unstable processes is less common. In this paper, systematic tuning methods are derived to tune the PID controller for unstable FOPTD(Forst Order Plus Time Delay) processes. The proposed PID controllers for set-point tracking and disturbance rejection problem are tuned based on minimizing the performance indexes (IAE, ISE, ITAE) using a real-coded genetic algorithm. Simulation example is given to illustrate the set-point tracking and disturbance rejection performance of the proposed method.

• Journal of Advanced Marine Engineering and Technology
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• v.37 no.1
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• pp.85-90
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• 2013

PID control for unstable processes with time delay is not easy to apply because of unstability due to the poles existing on left-hand side in s-plane and the effect of time delay. In this paper, the authors consider the PID controller design technique in case of predefining overshoot or rising time by designer according to control environment. To deal with constraint problem like this, in this paper, the RCGA incorporating the penalty strategy is used. This is the method that if the RCGA violates given constraints, the defined penalty function is summed to the evaluation function depending on the severity and then the given constraint problem is converted to non-constraints optimization problem. The proposed method is applied to the unstable FOPTD(First Order Plus Time Delay) system and simulations are accomplished to illustrate the set-point tracking performance.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.13 no.6
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• pp.284-289
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• 2003

The electric furnace, inside which the desired temperature is kept by the generated heat, is known to be a difficult system to control and model exactly because system parameters and response delayed time are varied as the temperature and positions are changed. In this study, the GPCEW (generalized predictive control with exponential weight), which always guarantees the stability of the closed loop system and can be effectively applied to the internally unstable system, was introduced to the ceramic drying electric furnace and was verified by showing its temperature tracking performance experimentally.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.980-986
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• 2002

In the fast data communication system, synchronized by a clock source, the loss of data will often occur due to several reasons as a differential routing path between data and clock, a differential propagation delay of components or an unstable phase of clock and data by external noise. In this paper, we describe the ASIC implementation of the data compensation circuit which can detect the data loss from above problems and recovery to original data with stable synchronization. Especially it supports a strong stability and a good BER in the communication system for fast data transfer as optic area. This circuit is implemented by Verilog HDL and available to the digital ASIC implementations related to fast data transfer.