• 베이커리
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• no.4 s.441
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• pp.158-161
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• 2005

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.1
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• pp.63-70
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• 2015

In this paper, a receiver has been developed in a $0.11-{\mu}m$ CMOS technology for 900 MHz RFID communication system applications. The receiver is composed of an envelope detector, a low-pass-filter, a comparator, D flip-flops, as well as an oscillator to provide the clock for digital blocks. The receiver is designed for low power consumption, which would be suitable for passive RFID tags. In this circuit, a digital data slicer was employed instead of the conventional analog data slicer in order to reduce the power consumption. The clock frequency is 1.68 MHz and the circuit operates with a power consumption as small as $5{\mu}W$. The chip size is $325{\mu}m{\times}290{\mu}m$ excluding the probing pads.

• Journal of IKEEE
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• v.14 no.1
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• pp.33-39
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• 2010

In this paper, a 5Gb/s receiver with an adaptive equalizer for serial link interfaces is proposed. For effective gain control, a least-mean-square (LMS) algorithm was implemented with two internal signals of slicers instead of output node of an equalizing filter. The scheme does not affect on a bandwidth of the equalizing filter. It also can be implemented without passive filter and it saves chip area and power consumption since two internal signals of slicers have a similar DC magnitude. The proposed adaptive equalizer can compensate up to 25dB and operate in various environments, which are 15m shield-twisted pair (STP) cable for DisplayPort and FR-4 traces for backplane. This work is implemented in $0.18-{\mu}m$ 1-poly 4-metal CMOS technology and occupies $200{\times}300{\mu}m^2$. Measurement results show only 6mW small power consumption and 2Gbps operating range with fabricated chip. The equalizer is expected to satisfy up to 5Gbps operating range if stable varactor(RF) is supported by foundry process.

• Journal of the Korean Society of Food Culture
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• v.2 no.2
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• pp.163-167
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• 1987

To determine and improve the holding machinery for the productin of convenient food (Dosirak) making Compnay in Seoul and Kyeongkido, a survey was conducted of 16 relative companys in 1986. The majority of the holding machinery are composed to work table, sink, rice cooker and fryer. It is necessary that the machinery are reinforced like packaging machine, air cleaner, cold and refrigeration room, sanitary arrangements.

• Proceedings of the Korea Information Processing Society Conference
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• 2019.05a
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• pp.342-345
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• 2019

드론의 동작 검증을 위한 테스트는 최종적으로 드론이 운용될 환경에서 이루어진다. 그러나 테스트 비용이 크고 테스트 비행 중 파손의 위험이 있기 때문에 시뮬레이션을 통한 사전 검증을 수행하는 것이 중요하다. 시뮬레이션은 SIL 방식이나 HIL 방식으로 이루어지는데 추가적인 외부 센서를 활용하는 경우 검증하기가 어렵다. SIL에서는 검증을 위해 가상의 외부 센서 구현이 필요하다. HIL 에서는 실제 센서를 사용하므로 가상의 외부 센서 구현은 필요 없다. 그러나 테스트 환경이기 때문에 실제 환경과 비슷한 데이터나 동작 검증에 적합한 데이터를 얻기 어렵다. 이러한 HIL에서의 문제를 해결하기 위해 외부 센서를 실제 환경에서 사용한 로그나 테스트 환경에서 센서 검증에 사용한 로그를 이용할 수 있다. 본 논문에서 제안하는 외부 센서의 로그를 활용한 HIL 시뮬레이션 기법 확장 내용은 외부 센서 데이터 입력기가 로그로부터 얻은 센서 데이터를 비행 컨트롤러로 보내 검증을 수행하기 때문에 데이터를 재사용할 수 있고 테스트 비용을 줄일 수 있다. 또 외부 센서 데이터 입력기는 로그 파서, 뷰어, 슬라이서, 데이터 전송기로 구성되어 로그로부터 검증에 적합한 데이터를 쉽게 얻어 활용할 수 있다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.9C
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• pp.891-897
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• 2003

Partial response maxim likelihood (PRML) is a powerful and indispensable detection scheme for perpendicular magnetic recording channels. The performance of PRML can be improved by incorporating a noise prediction scheme into branch metric computations of Viterbi algorithm (VA). However, the systems constructed by VA have shortcomings in the form of high complexity and cost. In this connection, a new simple detection scheme is proposed by exploiting the minimum run-length parameter d=1 of RLL code. The proposed detection scheme have a slicer instead of Viterbi detector and a noise predictor as a feedback filter. Therefore, to improve BER performance, the proposed detection scheme is extended to dual detection scheme for improving the BER performance. Simulation results show that the proposed scheme has a comparable performance to noise-predictive maximum likelihood (NPML) detector with less complexity when the partial response (PR) target is (1,2,1).

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.71-79
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• 2013

This paper describes a 12.5 Gb/s low-power receiver design with equalizer adaptation. The receiver adapts to channel and chip process variation by adaptation circuit using sampler and serializer. The adaptation principle is explained. It describes technique receiving ground referenced differential signal of voltage-mode transmitter for low-power. The CTLE(Continuous Time Linear Equalizer) having 17.6 dB peaking gain to remove long tail ISI caused channel with -21 dB attenuation. The voltage margin is 210 mV and the timing margin is 0.75 UI in eye diagram. The receiver consumes 0.87 mW/Gb/s low power in 45 nm CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.28-34
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• 2010

In this paper, the transceiver for RFID reader using 13.56MHz as a carrier frequency and meeting International Standard ISO 14443 type A, 14443 type B and 15693 is presented. The receiver is composed of envelope detector, VGA(Variable Gain Amplifier), filter, comparator to recovery the received signal. The proposed automatic reference voltage generator, positive peak detector, negative peak detector, and data slicer circuit can adjust the decision level of reference voltage over the received signal amplitudes. The transmitter is designed to drive high voltage and current to meet the 15693 specification. By using inductor loading circuit which can swing more than power supply and drive large current even under low impedance condition, it can control modulation rate from 30 percent to 5 percent, 100 perccnt and drive the output currents from 5 mA to 240 mA depending on standards. The 13.56 MHZ RFID reader is implemented in $0.18\;{\mu}m$ CM08 technology at 3.3V single supply. The chip area excluding pads is $1.5mm\;{\times}\;1.5mm$.