• Journal of the Korean Society for Railway
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• v.19 no.6
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• pp.727-735
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• 2016

Smart transformers are effective at reducing the weight and increasing the efficiency of traction systems for railroad applications. A smart transformer generally consists of rectifier modules and the Dual-Active-Bridge (DAB) converter modules. The efficiency of the smart transformer depends on not only the electrical characteristics, but also on the control method of the converter modules. Especially, a DAB converter has a high order degree of freedom of voltage modulation to control the power transferred through the high frequency transformer, and a voltage modulation method, are very critical for the efficiency of the DAB converter. This paper proposes a new voltage modulation method for the DAB converter to increase the efficiency in the low/medium power transfer condition. The proposed modulation method controls the reactive power in the high frequency transformer, making it zero. And, the switching loss is dramatically reduced by using the received converter module as a diode rectifier. The feasibility of the proposed modulation method is verified by computer simulation of the 900Vdc DAB converter power control.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.4
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• pp.188-200
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• 2002

The WRR scheduling algorithm is widely used in ATM networks due to its simplicity and the low cost of hardware implementation. It guarantees minimum cell rate according to the weight of each queue. The fairness is a important factor for ABR service. That is, scheduling algorithm allocates network resources fairly to each VC. However, WRR algorithm shows worse performance on bursty traffic. Because it schedules input traffics according to predetermined weight, it can not satisfies fairness criteria, MCR plus equal share and Maximum of MCR or Max-Min share, defined by ATM Forum TM 4.1 specification. The Nabeshima et al algorithm is not adapt to network status rapidly because it is not compensate the weights of unused bandwidth to VCs and assign the unused bandwidth to VCs by RR method. In this paper, we propose a scheduling algorithm for satisfying the two fairness criteria, MCR plus equal share and Maximum of MCR or Max-Min share, among the six criteria defined by ATM Forum TM 4.1 specification. The WRR, Nabeshima et al, and the proposed scheduling algorithms are compared with respect to fairness and convergence time throughout experimental simulation. According to the simulation results, the proposed algorithm shows higher fairness and more rapid convergence than other algorithms.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.10
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• pp.90-99
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• 2009

In this paper, we proposed the new class-E frequency multiplier design that include the highest efficient characteristics. The proposed frequency multiplier is designed for 5.8[GHz] output using the frequency multiplier about 2.9[GHz] input signal. And studying in this paper is for the design and the implementation of the class E frequency multiplier. For the result, the maximum highest efficient characteristics 32[%] which is with output power 24.5[dBm] and 8.5[dB], is shown with frequency multiplier for the 2.9/5.8[GHz] class E. And we applied the linear method to the implemented class E frequency multiplier. As a result, the output spectrum for the linear is upgrade to 12[dB], 12[dB], 13[dB] of the ACPR characteristics on the +11[MHz], +20[MHz], +30[MHz] offset frequency in the center frequency. The result is satisfied with the 3.83[%] of the lineared EVM for the 64-QAM modulated method with the 54[Mbps] transmission velocity. In this paper, we show that the good compensation result of the linearity and the efficiency through the digital pre-linear method of the distortion with the frequency multiplier. Therefore, we suggested the frequency multiplier method are applying to WLAN, cellular, PCS, WCDMA, and etc.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.1
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• pp.47-56
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• 1999

As the density of logic gates of VLSI chips has rapidly increased, more number of I/O pins has been required. This results in bigger package size and higher packager cost. The package cost is higher than the cost of bare chips for high I/O count VLSI chips. As the density of logic gates increases, the reduction method of the number of I/O pins for a given complexity of logic gates is required. In this paper, we propose the novel I/O interface circuit using CTR (Constant-Transition-Rate) code to reduce 50% of the number of I/O pins. The rising and falling edges of the symbol pulse of CTR codes contain 2-bit digital data, respectively. Since each symbol of the proposed CTR codes contains 4-bit digital data, the symbol rate can be reduced by the factor of 2 compared with the conventional I/O interface circuit. Also, the simultaneous switching noise(SSN) can be reduced because the transition rate is constant and the transition point of the symbols is widely distributed. The channel encoder is implemented only logic circuits and the circuit of the channel decoder is designed using the over-sampling method. The proper operation of the designed I/O interface circuit was verified using. HSPICE simulation with 0.6 m CMOS SPICE parameters. The simulation results indicate that the data transmission rate of the proposed circuit using 0.6 m CMOS technology is more than 200 Mbps/pin. We implemented the proposed circuit using Altera's FPGA and confimed the operation with the data transfer rate of 22.5 Mbps/pin.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.65-72
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• 2008

This paper proposes a new dual-loop digital PLL(DPLL) using seamless frequency tracking methods. The dual-loop construction, which is composed of the coarse and fine loop for fast locking time and a switching noise suppression, is used successive approximation register technique and TDC. The proposed DPLL in order to compensate the quality of jitter which follows long-term of input frequency is newly added cord conversion frequency tracking method. Also, this DPLL has VCO circuitry consisting of digitally controlled V-I converter and current-control oscillator (CCO) for robust jitter characteristics and wide lock range. The chip is fabricated with Dongbu HiTek $0.18-{\mu}m$ CMOS technology. Its operation range has the wide operation range of 0.4-2GHz and the area of $0.18mm^2$. It shows the peak-to-peak period jitter of 2 psec under no power noise and the power dissipation of 18mW at 2GHz through HSPICE simulation.

• Journal of the Korea Computer Industry Society
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• v.8 no.2
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• pp.107-112
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• 2007

Laser wave length can have evaporation effect by absorption because outer skin or tissue of focus is consisted of water almost though absorption of water occurs more than 90% almost in formation thickness of very thin floor. Can operate outer skin, steam by floor and correct incision of formation is available. Suture surgical operation is available to vein or lymph system and surgical operation region can dry and see as eye and radish bleeding surgical operation is available. Specially, stability of tube both end output about pulse by weight very, this research can cause various curative effect because can reduce bulk and control easily current wave style of medical laser using electric power conversion device of high frequency way. If introduce ZVS (Zero Voltage Switching) or ZVZCS (Zero Voltage and Zero Current Switching), is more profitable because can reduce switching damage. Because electric power department of proposed medical laser can do stable soft-switching in wide subordinate extent introducing ZVZCS technique by the first help and control department composes microcontroller, output current waveform user have free form make Result that experiment because design and manufacture, brought result that improve of 20% than existing equipment, and will be bought to get into superior result if supplement as systematic late.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.43 no.8
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• pp.757-764
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• 2015

Mathematical modeling of focal plane compensation device in the small earth-observation satellite camera has been conducted experimently for compensation of micro-vibration disturbance. The PZT actuators are used as control actuators for compensation device. It is quite difficult to build up mathematical model because of hysteresis characteristic of PZT actuators. Therefore, the compensation device system is assumed as a $2^{nd}$ order linear system and modeled by using MATLAB System Identification Toolbox. It has been found that four linear models of compensation device are needed to meet 10% error in the input frequency range of 0~50Hz. These models describe accurately the dynamics of compensation device in the 4 divided domains of the input frequency range of 0~50Hz, respectively. Micro-vibration disturbance can be compensated by feedback control strategy of switching four models appropriately according to the input frequency.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.10
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• pp.319-330
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• 2016

Recently, 3D printing technology has been applied to make a concept model and working mockup of an industrial application. On the other hand, this technology has limited applications in industrial products due to the materials and reliability of the 3D printed product. In this study, the components of a full cord switch module are proposed as a case of a 3D printed component that can be used as a substitute for a short period. These are hub-driven and lever lockup components that have the structural characteristics of breaking down frequently in the emergency operating status. To ensure the structural strength for a substitute period, research of structure optimization was performed because 3D printing technology has a limitation in the materials used. After optimizing the structure variables of the hub-driven component, reasonable results can be drawn in that the safety factors of the left and right switching mode are 1.243 (${\Delta}153.67%$) and 3.156 (${\Delta}404.96%$). The lever lockup component has a structural weak point that can break down easily on the lockup-part because of a cantilever shape and bending moment. The rib structure was applied to decrease the deflection. In addition, optimization of the structural variables was performed, showing a safety factor of 7.52(${\Delta}26%$).

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.454-464
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• 2023

This paper proposes a low-power 8-bit asynchronous SAR ADC with a sampling rate of 1 MS/s for sensor node applications. The ADC uses bootstrapped switches to improve linearity and applies a VCM-based CDAC switching technique to reduce the power consumption and area of the DAC. Conventional synchronous SAR ADCs that operate in synchronization with an external clock suffer from high power consumption due to the use of a clock faster than the sampling rate, which can be overcome by using an asynchronous SAR ADC structure that handles internal comparisons in an asynchronous manner. In addition, the SAR logic is designed using dynamic logic circuits to reduce the large digital power consumption that occurs in low resolution ADC designs. The proposed ADC was simulated in a 180-nm CMOS process, and at a 1.8 V supply voltage and a sampling rate of 1 MS/s, it consumed 46.06 𝜇W of power, achieved an SNDR of 49.76 dB and an ENOB of 7.9738 bits, and obtained a FoM of 183.2 fJ/conv-step. The simulated DNL and INL are +0.186/-0.157 LSB and +0.111/-0.169 LSB.