• Journal of IKEEE
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• v.27 no.4
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• pp.617-623
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• 2023

With the evolution of communication networks, there is a growing demand for stable high-speed data connections to support services relying on large-capacity data. The increasing volume of packet data aggregated from user devices underscores the significance of quality diagnostics for the backhaul network, an intermediate link transmitting data to the core network. This paper conducts empirical research on techniques to diagnose issues within the backhaul network through practical case studies, through diagnosing various factors such as circuit bandwidth, speed disparities within switches, network segment-specific buffer sizes, routing policies, among other factors that could potentially cause RTT (Round Trip Time) delays and performance degradation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.149-155
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• 2015

This paper proposes 5-MS/s 10-bit digital-to-analog converter(DAC) with the improved linearity. The proposed DAC consists of a 10-bit R-2R-based DAC, an output buffer using a differential voltage amplifier with rail-to-rail input range, and a band-gap reference circuit for the bias voltage. The linearity of the 10-bit R-2R DAC is improved as the resistor of 2R is implemented by including the turn-on resistance of an inverter for a switch. The output voltage range of the DAC is determined to be $2/3{\times}VDD$ from an rail-to-rail output voltage range of the R-2R DAC using a differential voltage amplifier in the output buffer. The proposed DAC is implemented using a 1-poly 8-metal 130nm CMOS process with 1.2-V supply. The measured dynamic performance of the implemented DAC are the ENOB of 9.4 bit, SNDR of 58 dB, and SFDR of 63 dBc. The measured DNL and INL are less than +/-0.35 LSB. The area and power consumption of DAC are $642.9{\times}366.6{\mu}m^2$ and 2.95 mW, respectively.

• The KIPS Transactions:PartC
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• v.10C no.1
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• pp.45-50
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• 2003

Guaranteed Frame Rate (GFR) service category is one of the most recent ATM service categories. The GFR specification was recently finalized by the ATM Forum and is expected to become an important service category which can efficiently support TCP/IP traffic in ATM network. In GFR switch implementation, it is important to guarantee MCR (minimum cell rate) and improve fairness. In this paper, we propose a new scheduling algorithm for the GFR service. Proposed algorithm provides priority to VC (virtual circuit)s and high Priority given to a VC which has fewer untagged cells in buffer. High priority VCs are serviced before low priority VCs. Proposed algorithm can guarantee MCR and improve fair sharing of the remaining bandwidth between GFR VCs. From computer simulation results, we demonstrate the proposed scheduling algorithm provide much better performance in TCP goodput and fairness than previous schemes.

• Journal of the Korea Society of Computer and Information
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• v.7 no.2
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• pp.101-114
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• 2002

The real multimedia application in wide area communication needs the guaranteed performance of communication service. Therefore, the resource is reserved at the moment of traffic burst and the region of connection admission possibility is widened at the basis of maximum cell rate. This of study shows that the end-to-end traffic delay to the traffic of burst state is guaranteed when the total of maximum transmission rate is higher than link speed by using the region of deterministic delay. The network load rate of connection admission can be improved by the inducement of delay bounds consideration each traffic characteristic to guarantee the end-to-end delay of network from single switch. This suggested buffering system using deterministic service do not give any influence to service quality and can guarantee the bounds of end-to-end delay. And it can also reduce the load of network even if the delay is increased according to the burst traffic characteristic. The above suggested system can be applied effectively to the various kinds of general network specification which admit both real time trafnc service and non-real time traffic service.

• The Transactions of the Korea Information Processing Society
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• v.7 no.11S
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• pp.3723-3731
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• 2000

Recently, the growth of applications and services over high-speed Internet increase, ATM networks as wide area back-bone has been a major solution. The conventional TCP suite is still the standard protocol used to support upper application on current Internet and uses a window based protocol for flow control in the transport layer. When TCP data uses the UBR service in ATM layer, the control method is also buffer management. If a cell is discarded in ATM layer. one whole packet of TCP will be lost. Which is responsible for most TCP performance degradation and do not offer sufficiently QoS. To solve this problem, Several dropping strategies, such as Tail Drop, EPD, PPO, SPD, FBA, have been proposed to improve the TCP performance over ATM. In this paper, to improve the TCP fairness of end to end, we propose a packet dropping scheme algorithm using two fixed threshold. Under similar condition, we compared our proposed scheme with other dropping strategies. Although the number of VC is increased, simulation results showed that the proposed scheme can allocate more fairly each VC than other schemes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.2
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• pp.47-55
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• 2012

A discrete-time(DT) filter with high-order temporal moving average(TMA) using actively-weighted charge sampling is proposed in this paper. To obtain different weight of sampled charge, the variable transconductance OTA is used prior to charge sampler, and the ratio of charge can be effectively weighted by switching the control transistors in the OTA. As a result, high-order TMA operation can be possible by actively-weighted charge sampling. In addition, the transconductance generated by the OTA is relatively accurate and stable by using the size ratio of the control transistors. The high-order TMA filter has small size, increased voltage gain, and low parasitic effects due to the small amount of switches and sampling capacitors. It is implemented in the TSMC $0.18-{\mu}m$ CMOS process by TMA-$2^2$. The simulated voltage gain is about 16.7 dB, and P1dB and IIP3 are -32.5 dBm and -23.7 dBm, respectively. DC current consumption is about 9.7 mA.