• Proceedings of the KIPE Conference
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• 2012.11a
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• pp.71-72
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• 2012

본 논문은 승압형 플라이백 컨버터에 탭을 내어 절연형 스위치드 커패시터셀과 차지펌프를 추가한 새로운 토폴로지의 컨버터를 제안한다. 제안하는 회로는 차지펌프를 추가한 스위치드 커패시터 셀의 출력과 플라이백의 출력을 직렬 연결하여 기존의 스위치드 커패시터 플라이백 컨버터보다 고승압에 유리하다. 또한 3차권선이 아닌 탭을내어 사용함에 있어 결합계수의 손실이 적어 고효율의 전력전달이 가능하다. 제안된 회로의 동작원리를 설명하였고 80W급 하드웨어 프로토 타입을 이용하여 검증하였다.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.353-354
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• 2012

본 논문은 동축권선 변압기를 이용한 승압형 플라이백 컨버터에 절연형 스위치드 커패시터 셀을 추가한 새로운 토폴로지를 제안한다. 제안하는 회로는 절연형 스위치드 커패시터 셀의 출력과 플라이백의 출력을 직렬 연결하여 고승압에 유리하고 스위치 온타임과 스위치 오프타임 모두 전력을 전달하여 기존의 플라이백 컨버터보다 향상된 변압기의 이용률을 가진다. 제안된 회로의 동작원리를 설명하고 60W급 하드웨어 프로토 타입을 이용하여 검증하였다.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.172-173
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• 2017

본 논문은 벅 차동전력조절 회로가 적용 된 다출력 스위치드-커패시터 부스트 컨버터의 소신호 모델 분석에 대한 논문이다. 제안하는 회로는 각 태양광 모듈의 최대전력점을 추정하기 위해서 제어된다. 제안하는 회로는 상태 공간 평균화 기법과 시그널 플로우 그래프를 통해서 해석하였으며 PSIM과 MATLAB을 통해서 증명하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.9
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• pp.1763-1770
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• 2016

This paper proposed hybrid converter to operate over a wide output load power. The switched-capacitor converter has a high efficiency at low load power and a low efficiency at high load power. On the contrary, the buck converter has a high efficiency at high load power and a low efficiency at low load power. The proposed hybrid converter has combination of the switched-capacitor converter and the buck converter. The switched-capacitor operates at low load power and buck converter operates at high load power, so that the hybrid converter is improved power efficiency at wide output load power. The hybrid converter was implemented with a $0.18{\mu}m$ CMOS process. The hybrid converter has a range of the load power between $50{\mu}W$and 100mW. The maximum power efficiencies are 93% and 77% at the buck converter and the switched-capacitor converter, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.9
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• pp.1755-1762
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• 2016

In this paper, a small areal dual-output SC(switched capacitor) DC-DC converter with a improved range of an input voltage is presented. The conventional SC DC-DC converter has an advantage of low cost and small chip area. But, it has a narrow input voltage range to convert efficiently. Also, it has a lager chip area and a lower power efficiency from multiple outputs. The proposed SC DC-DC converter improves the power efficiency by using the capacitor array structure which efficiently converts the voltage according to the input voltage. By sharing two switch array, it reduces the number of switches and capacitors from 32 to 25. The proposed SC DC-DC converter was manufactured in a $0.18{\mu}m$ CMOS process. In the simulation, the range of the input voltage is 0.7~ 1.8V, the max. power efficiency is 90%, and the chip area is $0.255mm^2$.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.485-488
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• 2000

In this paper dynamic analyses and control design of a step-down switched-capacitor dc-dc converter are presented. Open-loop dynamics of the converter are analyzed using the stage-space averaging technique. A systmatic control design method that offers excellent closed-loop performance for the converter is proposed, The analysis results and dynamic performance of the converter are verified using 18 W experimental converter that delivers a 5V/3.5V output from a 11-16V input source.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.12
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• pp.4984-4990
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• 2010

In this paper, a Step-down CMOS DC-DC Converter using low power switched capacitor method is designed in a 0.5 ${\mu}m$ technology for the integration of devices. Conventional DC-DC converter is used inductor that can store energy in a magnetic field but have low efficiency because power consumption is caused by magnetic flux. And there were problems with size, weight and price to integrate chip. In this paper, a proposed Inductorless step-down CMOS DC-DC converter of low power using SC method is designed in a 0.5um technology to solve these problems. Designed DC-DC converter have 96% power efficiency with 200kHz frequency by using cadence simulation.