• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2691-2697
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• 2010

Shader instructions and Compiler are designed for supporting 3D graphic shader 3.0 API. Variable-length instructions are proposed to reduce the size of hardware of graphic processor in SIMD structure by shortening the length of instructions. The designed shader compiler supports variable and two phased structured instructions, and can be programmable at ESSL level. Conformance Test proposed by Khronos group is accomplished to verify the design result of instructions and complier. The test result shows overall average 37% performance improvement at the 16 functions of basic GL shader.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.281-284
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• 2008

Recently, Khronos institude OpenGL ES 2.0 API for support Shader 3.0 model that can possible variable graphic processing. For this reason, the mobile device have need of supporting processor for a shader 3.0 model. We should extend instruction's length to support OpenGL ES 2.0 API, so we need more memory size. In this paper, we propose a new instruction form that adopted variable length and unit instruction architecture. This proposed instruction architecture that support to Shader 3.0 model has consist of 32bit unit instructions up to 4 which can be combined for embellishing each other. Therefore, it can execute flexible instruction combination and reduce waste of instruction fields.

• Journal of IKEEE
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• v.13 no.2
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• pp.253-259
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• 2009

In this paper, we propose a novel architecture of a general graphics shader processor without a dedicated hardware. Recently, mobile devices require the high performance graphics processor as well as the small size, low power. The proposed shader processor is a GP-GPU(General-Purpose computing on Graphics Processing Units) to execute the whole OpenGL ES 2.0 graphics pipeline by using shader instructions. It does not require the separate dedicate H/W such as rasterization on this fully programmable capability. The fully programmable 3D graphics shader processor can reduce much of the graphics hardware. The chip size of the designed shader processor is reduced 60% less than the sizes of previous processors.

• Journal of IKEEE
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• v.12 no.2
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• pp.118-123
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• 2008

The Khronos group releases OpenGL ES 2.0 API specification bringing streamlined shader programming to graphics processor of embedded system. For this reason, the mobile devices have need of graphics processor for supporting a OpenGL ES 2.0 API. We need to extend instruction`s length to support OpenGLES 2.0 API, so it needs more memory size. In this paper, we propose a new instruction format that offers availability for use the instructions. This proposed instruction adopt a variable length method and unit instruction architecture. This proposed instruction architecture that support to OpenGLES 2.0 API has consist of 32bit unit instructions up to 4 which can be combined for embellishing each other. Therefore, it can execute flexible instruction combination and reduce waste of instruction fields.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2675-2680
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• 2010

Computation steps for 3D graphic processing consist of two stages - fixed operation stage and programming required stage. Using this characteristic of 3D pipeline, a hybrid structure between graphics hardware designed by fixed structure and programmable hardware based on instructions, can handle graphic processing more efficiently. In this paper, fragment Shader is designed under this hybrid structure. It also supports OpenGL ES 2.0. Interior interface is optimized to reduce the delay of entire pipeline, which may be occurred by data I/O between the fixed hardware and the Shader. Interior register group of the Shader is designed by an interleaved structure to improve the register space and processing speed.

• Journal of IKEEE
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• v.12 no.4
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• pp.246-254
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• 2008

This paper represents a design of a 4 way SIMD processor with multi-thread and dual phase instruction pipeline. 8 threads can be performing in round-robin order, so any hazards can’t occur. The dual phase pipeline makes a pipeline operate as two pipelines, and it can fetch maximum 4 unit instructions at once. This variable length instruction set divide into first phase and second phase instructions, and with this function, complex branch and addressing can be executed at one clock cycle. This processor reduces the code size to quarter, pull out the doubled performance improvement than normal SIMD architecture.

• Journal of the Korea Computer Graphics Society
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• v.8 no.3
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• pp.25-34
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• 2002

최근 프로그래밍이 가능한 그래픽스 프로세서(GPU)의 등장은 렌더링 속도의 향상은 물론 기존의 GPU가 할 수 없었던 다양한 그래픽스 계산을 효과적으로 수행할 수 있도록 해주고 있다. 이로 인하여 기존에 CPU 상에서 수행해야만 했던 그래픽스 계산들의 일부를 GPU 상에서 수행하도록 해주는 기법들에 대한 연구가 활발히 진행되고 있다. 본 논문에서는 선형식에 기반을 둔 여러 응용 문제들을 GPU 상에서 효율적으로 구현할 수 있도록 도와주는 쉐이더 코드 최적화 기법을 제안한다. 이 기법은 SIMD 형태의 병렬 처리 능력을 가진 버텍스 쉐이더의 명령어에 맞게 고안되었다. 본 기법의 활용 가능성을 보이기 위하여 미분 방정식을 풀기 위한 4차 런지-쿠타 방법, 선형방정식을 풀기 위한 가우스-자이델 방법, 자연스러운 유체 모델링을 위한 파동 방정식 등의 문제에 적용하여 보았다. 본 논문에서 제안한 최적화 기법은 버텍스 쉐이더 용 컴파일러 구현에 쓰일 수 있으며, 향후 프로그래밍이 가능한 GPU 상에서의 실시간 그래픽스 소프트웨어 개발에 유용하게 사용될 수 있을 것이다.

• Journal of IKEEE
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• v.16 no.4
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• pp.310-315
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• 2012

This thesis is intended to design multi thread mobile GPGPU optimized in mobile environment, and to verify an effective thread management method of the multi thread mobile processor. In thread management, there is no management hardware and implement with software instructions. For the verification of the multi thread management method, Lane detection algorithm was implemented to compare nVidia's CUDA Architecture and the designed GPGPU in terms of thread management efficiency. The number of thread is normalized to 48 threads. An implemented Land Detection Algorithm is composed of Gaussian filter algorithm and Sobel Edge Detection algorithm. As a result, the designed GPGPU's thread efficiency is up to 2 times higher than CUDA's thread efficiency.