• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.10 s.340
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• pp.55-64
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• 2005

In this paper, we designed floating point units to accelate real-time 3D Graphics for Geometry processing. Designed floating point units support IEEE-754 single precision format and we confirmed 100 MHz performance of floating point add/mul unit, 120 MHz performance of floating point NR inverse division unit, 200 MHz performance of floating point power unit, 120 MHz performance of floating point inverse square root unit at Xilinx-vertex2. Also, using floating point units, designed Geometry processor and confirmed 3D Graphics data processing.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06b
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• pp.476-481
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• 2007

큰 소수를 빠르게 생성하기 위한 다양한 소수 검사 방법이 개발되었으며, 가장 많이 쓰이는 소수 검사 방법은 trial division과 Fermat (또는 Miller-Rabin) 검사를 조합한 방법과 gcd 연산과 Fermat (또는 Miller-Rabin) 검사를 조합한 방법이다. 이 중 trial division과 조합한 방법에 대해서는 확률적 분석을 이용하여 수행시간을 예측하고 수행시간을 최적화 하는 방법이 개발되었다. 하지만, gcd 연산과 조합한 방법에 대해서는 아무런 연구결과도 제시되어 있지 않다. 본 논문에서는 gcd 연산을 이용한 조합 소수 검사 방법에 대해 확률적 분석을 이용하여 수행시간을 예측하고 수행시간을 최적화 하는 방법을 제안한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.809-811
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• 2010

In most floating-point operations related with 3D graphic applications for mobile devices, properly approximated data calculations with reduced complexity and low power are preferable to exactly rounded floating-point operations with unnecessary preciseness with cost. Among all the sophisticated floating-point arithmetic operations, multiplication and division are the most complicated and time-consuming, and they can be transformed into addition and subtraction repectively by adopting the logarithmic conversion. In this process, the most important factor for performance is how high we can make an approximation of the logarithm conversion. In this paper, we cover the trends in studying the logarithm conversion circuit designs. We also discuss the important factor in design issues and the applicable fields in detail.

• Journal of Elementary Mathematics Education in Korea
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• v.12 no.1
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• pp.1-25
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• 2008

The purpose of this study was to identify pre-service teachers' Pedagogical Content Knowledge (PCK) about decimal calculation. A written questionnaire was developed dealing with decimal calculation. A total of 152 pre-service teachers from 3 universities were selected for this study; they had taken an elementary mathematics teaching method course and had no teaching experience. The results were as follows: First, with regard to the method of decimal calculation, most pre-service teachers were familiar with algorithms introduced in the textbook. But with regard to the meaning of decimal calculations, they had difficulties in understanding decimal multiplication or decimal division with decimal number. Second, pre-service teachers recognized reasons of errors as well as errors patterns that student might make. But this recognition was limited mainly to errors related to natural number calculation. Third, pre-service teachers frequently commented about decimals algorithms, picture models, the meanings of decimal calculations, and connections to natural number calculations. Many of them represented the meanings of decimal calculations through picture models as to help students' understanding, while they just mentioned algorithms or treated decimal calculation as natural number calculations with decimal point.

• Journal of IKEEE
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• v.22 no.3
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• pp.805-809
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• 2018

In this paper, we analyze the change of accuracy when fixed point arithmetic is used instead of floating point arithmetic in binary weight network(BWN). We observed the change of accuracy by varying total bit size and fraction bit size. If the integer part is not changed after fixed point approximation, there is no significant decrease in accuracy compared to the floating-point operation. When overflow occurs in the integer part, the approximation to the maximum or minimum of the fixed point representation minimizes the decrease in accuracy. The results of this paper can be applied to the minimization of memory and hardware resource requirement in the implementation of FPGA-based BWN accelerator.

• Journal of Elementary Mathematics Education in Korea
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• v.15 no.1
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• pp.1-18
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• 2011

The purpose of this study was to investigate the effects of estimation strategy on placing decimal point in multiplication and division of decimals. To examine the effects of improving calculation ability and reducing decimal point errors with this estimation strategy, the experimental research on operation with decimal was conducted. The operation group conducted the decimal point estimation strategy for operating decimal fractions, whereas the control group used the traditional method with the same test paper. The results obtained in this research are as follows; First, the estimation strategy with understanding a basic meaning of decimals was much more effective in calculation improvement than the algorithm study with repeated calculations. Second, the mathematical problem solving ability - including the whole procedure for solving the mathematical question - had no effects since the decimal point estimation strategy is normally performed after finishing problem solving strategy. Third, the estimation strategy showed positive effects on the calculation ability. Th Memorizing algorithm doesn't last long to the students, but the estimation strategy based on the concept and the position of decimal fraction affects continually to the students. Finally, the estimation strategy assisted the students in understanding the connection of the position of decimal points in the product with that in the multiplicand or the multiplier. Moreover, this strategy suggested to the students that there was relation between the placing decimal point of the quotient and that of the dividend.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1997.10a
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• pp.233-236
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• 1997

퍼지 관계 개념을 응용한 퍼지 정보 검색은 형태론에 입각한 기존의 정보 검색과는 달리 문서와 용어의 의미론에 근거하는 정보검색을 할 수 있다. 퍼지 정보 검색은 문헌의 집합 용어의 집합으로 나누고 문헌과 용어의 관계성을 문서 $\times$ 용어이 관계 행렬로 나타내며 퍼지 관계곱 연산을 이용하여 시소러스(thesaurus)를 형성하고 사용자로부터 주어진 질의 적합한 문서를 제공한다. 그러나 이러한 퍼지 관계곱 연산은 매우 큰 시간 복합도를 요구하는 연산이고 퍼지값은 부동소수점으로 표현해야하므로 대용량의 문서 시스템에 적용할 수 없어 비현실적이다. 부동소수점 연산은 연산속도가 느리고 저장공간도 많이 요구하므로 부동소수점 연산을 비트 연산으로 대체할 수 있다면 처리속도와 처리공간에 있어 성능 향상을 기대할 수 있다. 본 연구는 퍼지 정보 검색의 시소러스 형성에 있어 $\alpha$-cut 적용의 시기를 조정하여 성능을 향상하는 방법을 제안한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.886-889
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• 2006

수치연산 보조프로세서로도 알려져 있는 부동 소수점 연산장치(FPU)는 컴퓨터가 사용하는 기본 마이크로프로세서보다 더 빠르게 숫자를 다를 수 있는 특별한 회로 설계 또는 마이크로프로세서를 말한다. FPU는 전적으로 대형 수학적 연산에만 초점을 맞춘 특별한 명령 셋을 가지고 있어서 그렇게 빠르게 계산을 수행할 수 있는 것이다. FPU는 오늘날의 거의 모든 PC에 장착되고 있지만, 실은 그것은 그래픽 이미지 처리나 표현 등과 같은 특별할 일을 수행할 때에 필요하다. 초창기 컴퓨터 회사들은 각기 다른 연산방식을 사용했다. 이에 따라 연산결과가 컴퓨터마다 다른 문제점을 해결하기 위해 IEEE에서는 부동 소수점에 대한 표준안을 제안하였다. 이 표준안은 IEEE Standard 754 이며, 오늘날 인텔 CPU 기반의 PC, 매킨토시 및 대부분의 유닉스 플랫폼에서 컴퓨터 상의 실수를 표현하기 위해 사용하는 가장 일반적인 표현 방식으로 발전하였다. 본 논문에서는 부동 소수점 표준안 중 32-bit 단일 정밀도 부동 소수점 가산기를 VHDL로 구현하여 FPGA칩으로 다운하고 PCI 인터페이스를 통해 Visual C++로 데이터의 입출력을 검증하였다.

• Journal of Elementary Mathematics Education in Korea
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• v.11 no.1
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• pp.1-21
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• 2007

The purpose of this study was to propose instructional methods using base-ten blocks in teaching the multiplication of decimal for 5th grade students by analyzing the process of their conceptual comprehension of multiplication of decimal. The students in this study were found to understand various meanings of operations (e.g., repeated addition, bundling, and area) by modeling them with base-ten blocks. They were able to identify the algorithm through the use of base-ten blocks and to understand the principle of calculations by connecting the manipulative activities to each stage of algorithm. The students were also able to determine whether the results of multiplication of decimal might be reasonable using base-ten blocks. This study suggests that appropriate use of base-ten blocks promotes the conceptual understanding of the multiplication of decimal.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8B
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• pp.1460-1468
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• 2000

The goal of this research is the real-time implementation of MPEG-1 Layer III audio decoder using the fixed-point digital signal processor of TMS320C6201 The main job for this work is twofold: one is to convert floating-point operation in the decoder into fixed-point operation while maintaining the high resolution, and the other is to optimize the program to make it run in real-time with memory size as small as possible. We, especially, devote much time to the descaling module in the decoder for conversion of floating-point operation into fixed-point operation with high accuracy. The inverse modified cosine transform(IMDCT) and synthesis polyphase filter bank modules are optimized in order to reduce the amount of computation and memory size. After the optimization process, in this paper, the implemented decoder uses about 26% of maximum computation capacity of TMS320C6201. The program memory, data ROM, data RAM used in the decoder are about 6.77kwords, 3.13 kwords and 9.94 kwords, respectively. Comparing the PCM output of fixed-point computation with that of floating-point computation, we achieve the signal-to-noise ratio of more than 60 dB. A real-time operation is demonstrated on the PC using the sound I/O and host communication functions in the EVM board.