• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.6
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• pp.303-309
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• 2012

Energy expenditure values were estimated based on the voice signals and body activities. Voice signals and body activities were obtained using PVDF contact vibration sensor and 3-axis accelerometer, respectively. Vibration caused by voices, activity signals, and actual energy consumption were acquired using data acquisition system and gas analyzer. With the use of power values from the voice signals and weight as independent variables, R-square of 0.918 appeared to show the highest value. For activity outputs, use of signal vector magnitude, body mass index, height, and age as independent variables revealed to provide the highest correlation with actual energy expenditure. Estimation of energy expenditure based on voice and activity provides more accurate results than based on activity only.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.43-49
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• 2009

We present an efficient estimation method of the battery lifetime considering various power consumption profiles in wireless sensor nodes. The power profiles in single and periodic modes and the current dissipations in different operating modes are taken into account to find the total current consumption. Also, the self-discharge rate of a battery is taken into account to estimate the battery lifetime of a given sensor node. Finally we present a governing equation for finding the battery lifetime. We believe the proposed estimation method of the battery lifetime can be an efficient and effective method for low power design of sensor nodes.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.2
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• pp.50-55
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• 2001

In this paper, a 8bit parity checker/generator is designed using a new gate which is proposed to implement the exclusive or(XOR) and exclusive-nor(XNOR) functions for low power consumption on transistor level. Conventional XOR/XNOR gate such as CPL, DPL and CCPL designed to reduce the power consumption has an inverter to get the full swing output signals. But this inverter consumes the major part of power and causes the time delay on CMOS circuits. Thus a new technique was adopted not utilizing inverter in the circuits. The results of simulation by Hspice shows 33% of power reduction compared with CCPL gate when A 8 bit parity checker was made with the proposed new gate using $0.8{\mu}mCMOS$ technology.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.3
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• pp.437-443
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• 2007

In this paper, we propose the power-aware test framework for Network-on-Chip, which is based on embedded processor and on-chip network. First, the possibility of using embedded processor and on-chip network isintroduced and evaluated with benchmark system to test the other embeddedcores. And second, a new generation method of test pattern is presented to reduce the power consumption of on-chip network, which is called don't care mapping. The experimental results show that the embedded processor can be executed like the automatic test equipments, and the test time is reduced and the power consumption is reduced up to 8% at the communication components.

• 전자공학회논문지 IE
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• v.48 no.2
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• pp.19-25
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• 2011

This paper presented neural network modeling method using vehicle data to predict fuel consumption. To acquire data for training and testing the proposed neural network, medium-class gasoline vehicle drove at downtown and parameters measured include speed, engine rpm, throttle position sensor (TPS), and mass air flow (MAF) as input data, and fuel consumption as target data from OBD-II port. Multi layer perception network was used for nonlinear mapping between the input and the output data. It was observed that the neural network model can predict the vehicle quite well with mean squared error was $1.306{\times}10^{-6}$ for the fuel consumption.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8B
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• pp.1477-1486
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• 2000

This paper proposes an efficient kernel-based partitioning algorithm for reducing area and power dissipation in combinational circuit design.. The proposed algorithm decreases the power consumption by partitioning a given circuit utilizing a kernel, and reduces the area overhead by minimizing duplicated gates in the partitioned subcircuits. Experimental results for the MCNC benchmarks show that the proposed algorithm is effective by generating circuits consuming 43.6% less power with 30.7% less area on the average, when compared to the previous algorithm based on precomputation circuit structure.

• The KIPS Transactions:PartA
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• v.16A no.1
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• pp.27-34
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• 2009

Recently, power saving with high performance is one of the hot issues in the mobile systems. Various technologies are introduced to achieve low-power processors, which include sub-micron semiconductor fabrication, voltage scaling, speed scaling and etc. In this paper, we introduce a new method that reduces of energy loss at the data cache. Our methods take the benefits in terms of speed and energy loss using selective way precharging of way prediction with concurrent way selecting. By the simulation results, our method achieves 10.2% energy saving compared to the way prediction method, and 56.4% energy saving compared to the common data cache structure.

• Journal of the Korea Society of Computer and Information
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• v.19 no.6
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• pp.61-69
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• 2014

Various Time Synchronization protocols considering for the characteristics of WSN(Wireless Sensor Network) have been developed, because a time relationship plays an important role in many WSN applications, as well. Synchronization accuracy as well as constraints of energy should be considered for WSN Time Synchronization protocols, especially. In this paper, I analyze Time Synchronization protocols for WSN after classifying these protocols with a new criteria (i.e. power consumption). So, this method will contribute to evaluating and comparing WSN Time Synchronization protocols in respect of power consumption.

• Journal of the Korea Society of Computer and Information
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• v.19 no.5
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• pp.1-10
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• 2014

The proposed scheme schedules given real-time tasks so that energy consumption of multicore processors would be minimized while meeting tasks' deadline and tolerating a permanent fault based on the primary-backup task model. Whereas the previous methods minimize the overlapped time of a primary task and its backup task, the proposed scheme maximizes the overlapped time so as to decrease the core speed as much as possible. It is analytically verified that the proposed scheme minimizes the energy consumption. Also, the proposed scheme saves up to 77% energy consumption of the previous method through experimental performance evaluation.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2015.07a
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• pp.46-48
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• 2015

본 논문은 외부 전원에 연결되었지만 본래의 용도(예: 셋톱박스인 경우 방송서비스 제공)로 사용되지 않는 대기상태에서도 기존 셋톱박스처럼 업데이트를 수행하면서도 기존의 셋톱박스에 비해 전력소모를 줄일 수 있는, 대기상태의 셋톱박스를 제어하는 방안을 제안한다. 본 논문의 제어방안은 셋톱박스로 전달되는 CPU 활성화 메시지를 이용하거나 메시지의 프로토콜의 일부만 분석하는 방법을 이용하여 셋톱박스 업데이트 필요 유무를 판별하는 방안으로 이는 낮은 CPU(Central Processing Unit) 연산 량만 필요로 하여 셋톱박스 전력소모 저감에 적합하다. 본 논문의 제어방안은 기존의 사업자 측면에서 대기상태 셋톱박스의 업데이트 편의성을 유지시키면서도 국가적 차원의 전력소모 저감에 기여를 할 것이다.