• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.24-30
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• 2010

In recent memories, repair is an unavoidable method to maintain its yield and quality. The probability of defect occurence on spare lines has been increased through the growth of the density of recent memories with 2 dimensional spare architecture. In this paper, a new analysis region virtualization scheme is proposed. the analysis region virtualization scheme can be applied with any BIRA (built-in redundancy analysis) algorithms without the loss of their repair rates. The analysis region virtualization scheme can be a viable solution for BIRA considering the faulty spare lines of the future high density memories.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.5
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• pp.21-29
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• 1999

이동횟수 기반 위치갱신 기법에서 고정망과의 접속은 단말 내부의 계수기가 이동횟수 임계치에 이르러 위치갱신이 수행되거나 신규호가 발생할 경우에 행해진다. 그러나 단말의 계수기가 임계치에 이르는 동시에 단말이 이전 위치갱신이 수행된 셀(중앙셀)로 재진입이 발생할 경우 불필요한 위치갱신이 수행된다. [2]에서는 중앙셀로 재진입이 발생하는 경우의 불필요한 위치갱신 수행을 제거하기 위해 중앙셀로 재진입이 발생할 경우 계수기를 영으로 초기화한다. 본 논문에서는 [2]의 기법을 일반화하여 위치갱신 비용을 절약할 수 있는 개선된 기법을 제안한다. 본 기법은 단말이 셀 사이를 이동하는 동안 단말은 자신이 방문한 셀과 이동횟수에 관한 정보를 저장한다. 단말이 이미 방문한 셀로 재진입이 발생할 겨우 이동횟수 계수기를 증가시키는 것이 아니라 이전 방문시 저장하였던 이동횟수로 재조정한다. 이러한 이동회수 계수기의 재조정 방법을 통하여 불필요한 위치갱신과 신호절차를 효과적으로 줄일 수 있다. [2]의 기법은 본 논문에서 제안하는 기법 중에서 중앙셀로 재진입할 때만 계수기를 영으로 재조정하는 특수한 경우에 해당된다. 본 기법이 전체 위치관리 비용을 크게 절약할 수 있음을 증명하기 위해 다양한 환경에서의 성능분석 및 수치적 결과를 통해 알아 본 결과 호 도착 비율당 전체 위치관리 비용이 평균 17-26% 절약됨을 관찰할 수 있었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.10
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• pp.865-873
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• 2013

In the cellular networks adopting femtocells, the macrocell users can suffer from severe interference by the femtocells. In this paper, we propose a distributed transmission power control scheme for femtocells to protect macrocell users. With the proposed scheme, when a macrocell user experiences outage due to severe interference, it informs the interfering femtocell base station (BS) of the outage occurrence, via the macrocell BS. Then, the femtocell BS reduces the transmission power to protect the macrocell user. The proposed scheme does not require too much control information among the macrocell BS, the macrocell users, and the femtocell BS. Moreover, the computational complexity in femtocell BS is very low. By using simulation, we show that the performance of the proposed scheme is good enough to use in practice, in spite of its simplicity.

• Journal of KIISE:Information Networking
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• v.27 no.3
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• pp.323-330
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• 2000

이동통신망의 발전으로 인해 한정적인 주파수 자원을 효율적으로 사용하여 폭증하는 가입자를 수용하기 위해 셀의 반경은 점점 작아지고 있다. 가입자에게 신규호의 실패보다 더 민감한 핸드오프호가 자주 발생함에 따라 핸드오프호 처리의 중요성이 증대되었다. 따라서, 셀마다 핸드오프호를 위한 예약 채널을 두어 어느 정도 신규호의 블록킹율의 증가를 감수하더라도, 핸드오프호의 강제종료율을 낮추는 방법이 제안되었다. 이러한 예약 채널 할당 기법에서는 예약 채널을 몇 개로 할 것인가가 중요한 문제가 된다. 왜냐하면 예약 채널 수를 과다하게 설정하면 핸드오프가 빈번하지 않은 셀에서는 채널의 낭비를 초래하고, 적게 설정하면 핸드오프가 빈번한 셀은 핸드오프 강제종료율이 높아지게 되기 때문이다. 이러한 문제를 해결하기 위해 본 논문은 신경망 모델 중 다층 퍼셉트론을 이용하여 셀에서 요구되는 최적의 예약율을 구하여 셀의 환경이 변할 때마다 적용할 수 있는 방법을 제안한다. 본 논문에서는 모의 실험을 통해 이동통신 시스템에서의 핸드오프 예약율을 주기적으로 최적화 시킴으로써 핸드오프가 자주 발생하는 셀에서는 핸드오프 강제종료율을 낮추고, 핸드오프가 빈번하지 않은 셀은 채널의 손실을 막아 시스템의 전체적인 효율이 향상됨을 보인다.

• Journal of the Korea Society of Computer and Information
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• v.7 no.3
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• pp.143-148
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• 2002

Congestion may take place in the ATM network because of high-speed cell transmission features, and cell delay and loss also can be caused by unexpected traffic variation. Thus, traffic control mechanisms are needed. One of them to decrease congestion is the Cell shaping. This paper proposes a hybrid type cell shaper composed of a Leaky Bucket with token pool, Tn with time window, and a spacing control buffer. The simulator BONeS with the ON/OFF traffic source model evaluates the performance of the proposed cell shaping method. Simulation results show that the cell shaping concerning the respective source traffics is adapted to and then controlled on the mean bit rate.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.1
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• pp.1-8
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• 2011

This study is about the limits of GTEM cell using correlation factor between the OATS(Open area Test Site) and the GTEM cell. First, the field strengths at the 10 m distance OATS and in GTEM cell to obtain the experimental correlation factor are measured. Also, the EMI limits of radiated power are derived in GTEM cell as 3 position method is inversely transformed. The field strengths that calculated from theoretical models by 3 and 15 position methods are programmed and compared with measured data at the OATS. As the EMI limits of GTEM cell is newly defined, it will be use to substitute GTEM cell for OATS to efficiently measure EMI(Electromagnetic Interference).

• Journal of IKEEE
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• v.1 no.1 s.1
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• pp.11-18
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• 1997

By utilizing the technique to monitor the DC cell node voltages through circuit simulation, degradation of the static read operating margin In high load-resistor SRAM cell was examined, which is caused by parasitic resistances and transistor asymmetries in this cell structure. By selectively adding the parasitic resistances to an ideal cell, the influence of each parasitic resistance on the operating margin was examined, and then the cases with parasitic resistances in pairs were also examined. By selectively changing the channel width of cell transistors to generate cell asymmetry, the influence of cell asymmetry on the operating margin was also examined. Analyses on the operating margins were performed by comparing the supply voltage values at which two cell node voltages merge to a single value and the differences of cell node voltages at VDD=5V in the simulated node voltage characteristics. By determining the parasitic resistances and the transistor asymmetries which give the most serious effect on the static read-operation of SRAM cell from this analysis based on circuit simulated, a criteria was provided, which can be referred in the design of new SRAM cell structures.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.12A
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• pp.1191-1199
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• 2008

We propose the Staggered-zone Resource Allocation (SRA) in order to relax throughput decrease problems by the co-channel interference of the cell boundary users at the cellular OFDMA system using frequency reuse factor K=1 and analyze the throughput improvement. The proposed algorithm allocates the resources to the users in compliance with resource allocation rule which is planned in order to minimize co-channel interference between cells without any additional information. The resource allocation method in the SRA lines up the users in pathloss order as descending series, and then allocates from pre-determined resource allocation region where decides differently in each cell. This algorithm prevents the co-channel interferences of the cell boundary user to be caused by using same resource simultaneously and equalizes interference to the users in the cell.

• The Transactions of the Korea Information Processing Society
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• v.1 no.4
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• pp.490-501
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• 1994

In this study the problems of cell marking method used in the field of ATM network traffic control are presented. Also an extended cell marking method considering the user level priority is proposed. The conventional traffic monitoring schemes set the CLP bit of a cell to 1 only under the circumstance of the violation of traffic contract. It causes that the number of low level cells increases and the levels of cells are lowered regardless of the user level priority. The three level priority control method combining FCI bit with CLP bit has also been proposed. It divides CLP=0 cells into two levels. Consequently, the proposed method preserves more cells in high level than the conventional one and the real loss of high level cells can be reduced. The performance of the proposed scheme has also been analyzed by the PBS(partial buffer sharing) with two thresholds for the proposed three levels. The result shows that the PBS with two thresholds can give more efficient control than the scheme with no priority, or the PBS with one threshold.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.10 s.340
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• pp.1-8
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• 2005

In this paper, a FRAM design style based on PMOS-gating cell structure is described. The memory cell consists of a PMOS access transistor and a ferroelectric capacitor. Its plate is grounded. The proposed scheme employs three novel operating methods: 1) $V_{DD}$ precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore, Because this configuration doesn`t need the on-pitch plate control circuitry, it is effective in realizing cost-effective chip sizes. Implementation for a 2.5-V, 1-Mb FRAM prototype design in a $0.25-{\mu}m$, triple-well technology shows a chip size of $3.22\;mm^{2}$, an access time of 48 ns and an active current of 11 mA. The cell efficiency is 62.52 $\%$. It has gained approximately $20\;\%$ improvement in the cell array efficiency over the conventional plate-driven FRAM scheme.