• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.43 no.1 s.307
• /
• pp.1-8
• /
• 2006

This thesis proposes Arithmetic Shift Register(ASR) which can be used as pseudo random number generator. Arithmetic Shift. Register is defined as progression that multiplies random number D , not 0 or 1 at initial value which is not 0, and it is represented as ASR-D in this thesis. Irreducible polynomial that t which makes $'D^k=1'$ satisfies uniquely as $'t=2^n-1'$ over. $GF(2^n)$ is the characteristic polynomial of ASR-D , and the cycle of Arithmetic Shift Register has maximum cycle as $'2^n-1'$. Galois Linear Feedback Shift Register corresponds to ASR-2-1. Therefore, Arithmetic Shift Register proposed in this thesis generalizes Galois Linear Feedback Shift Register. Linear complexity of ASR-D over$GF(2^n)$ is $'n{\leq}LC{\leq}\frac{n^2+n}{2}'$ and in comparison with existing Linear Feedback Shift Register stability is high. The Software embodiment of arithmetic shift register proposed in this thesis is efficient than that of existing Linear Shift Register and hardware complexity is equal. Arithmetic shift register proposed in this thesis can be used widely in various fields such as cipher, error correcting codes, Monte Carlo integral, and data communication etc along with existing linear shift register.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.12 no.3
• /
• pp.77-85
• /
• 2002

A Research of binary random sequence generator that uses a linear shift register had been studied since the 1970s. These generators were used in stream cipher. In general, the binary random sequence generator consists of linear shift registers that generate sequences of maximum period and a nonlinear filter function or a nonlinear combination function to generate a sequence of high linear complexity. Therefore, To generate a sequence that have long period as well as high linear complexity becomes an important factor to estimate safety of stream cipher. Usually, the maximum period of the sequence generated by a linear feedback shift register with L resistors is less than or equal to $2^L$-1. In this paper, we propose new binary random sequence generator that consist of L registers and 2 sub-characteristic polynomials. According to an initial state vector, the least period of the sequence generated by the proposed generator is equal to or ions than it of the sequence created by the general linear feedback shift register, and its linear complexity is increased too.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.24 no.1
• /
• pp.51-58
• /
• 2014

A LFSR is commonly used for various stream cryptography applications to generate random numbers. A Leap-ahead LFSR was presented to generate a multi-bits random number per cycle. It only requires a single LFSR and it has an advantages in hardware complexity. However, it suffers from the significant reduction of maximum period of the generated random numbers. This paper presents the new segmented Leap-ahead LFSR to solve this problem. It consists of two segmented LFSRs. We prove the efficiency of the proposed segmented architecture using the precise mathematical analysis. We also demonstrate the proposed comparison results with other counterparts using Xinilx Vertex5 FPGA. The proposed architecture can increase 2.5 times of the maximum period of generated random numbers compared to the typical Leap-ahead architecture.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.14 no.3
• /
• pp.235-239
• /
• 1989

A multiplier is proposed for computing multiplication of two arbitrary elements in the finite fields GF($2^m$), and the operation process is described step by step. The modified type of the circuit which is constructed with m-stage feedgack shift register, m-1 flip-flop, m AND gate, and m-input XOR gate is presented by referring to the conventional shift-register multiplier. At the end of mth shift, the shift-register multiplier stores the product of two elements of GF($2^m$); however the proposed circuit in this paper requires m-1 clock times from first input to first output. This circuit is simpler than cellulra-array or systolic multiplier and moreover it is faster than systolic multiplier.

• Proceedings of the KIEE Conference
• /
• 2009.07a
• /
• pp.1937_1938
• /
• 2009

이 논문에서는 1차원 혼돈맵들 중의 하나인 톱니맵을 8비트의 유한정밀도로 이산화시켜 설계하였고, 이 이산화된 톱니맵을 사용한 혼돈 2진 순서 발생기의 회로도도 제시하였다. 설계된 혼돈맵의 실제 구현은 이산화된 진리표로부터 얻어진 출력변수의 간략화된 부울함수에 따른 입력선과 출력선들의 정확한 연결만에 의해 실현하였다. 최대길이를 발생시키는 선형궤환시프트레지스터(mLFSR)에 의해 발생되는 난수성 2진 출력 순서들을 이산화된 톱니맵의 입력순서로 사용함으로써 결과적으로 최소 8배 더 긴 주기를 갖는 혼돈 2진 순서들을 발생시켰다.

• The Journal of the Korea Contents Association
• /
• v.8 no.7
• /
• pp.53-57
• /
• 2008

The discretized saw-tooth map with the 16-bit finite precision which is one of the 1-dimensional chaotic maps is designed, and the circuit of chaotic binary sequence generator using the discretized saw-tooth map is presented also in this brief. The real implementation of designed chaotic map is accomplished by connecting the input and output lines exactly according to the simplified Boolean functions of output variables obtained from truth table which is discretized. The random binary output sequences generated by mLFSR generator were used for the inputs of descretized saw-tooth map, and, by the descretized map, chaotic binary sequence which has more long period of 16 times minimally is generated as a results.