• Proceedings of the Korea Water Resources Association Conference
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• 2020.06a
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• pp.323-323
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• 2020

그래픽 처리 장치(Graphic Processing Unit: GPU)는 그래픽 처리 작업에 특화된 다수의 산술논리 장치(Arithmetic Logic Unit: ALU)로 구성되어 있어서 중앙 처리 장치(Central Processing Unit: CPU)보다 한 번에 더 많은 연산 수행이 가능하다. 본 연구는 GPU 가속 운동파모형을 실제 유역에 적용하여, GPU 가속 운동파 강우유출모형 결과에 대한 정확성과 연산 소요 시간에 대한 효율성을 확인하였다. GPU 가속 운동파모형은 분포형 강우유출모형의 수치모의 연산시간을 단축시키기 위해 CUDA 포트란을 이용하여 개발되었다. 분포형모형의 지배방정식은 운동파모형과 Green-Ampt모형으로 구성되었고, 운동파모형은 유한체적법을 이용하여 이산화 하였다. GPU 가속 운동파모형을 이용하여 금강의 미호천 유역에서 발생하는 강우유출현상을 모의 하였고, 동일한 유한체적법을 이용한 CPU(Central Processing Unit) 기반의 강우유출모형과 비교하였다. 그 결과 GPU 가속모형의 결과는 미호천 유역 하류단에서 관측한 결과와 유사한 결과를 나타냈다. 또한, 연산소요시간은 CPU 기반의 강우유출모형의 연산소요시간보다 단축되었으며, 본 연구에 사용된 장비를 기준으로 최대 100배 정도 단축되었다.

• Journal of Elementary Mathematics Education in Korea
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• v.21 no.1
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• pp.1-22
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• 2017

The properties of arithmetic are considered as essential to understand the principles of calculation and develop effective strategies for calculation in the elementary school level, thanks to agreement on early algebra. Therefore elementary students' misunderstanding of the properties of arithmetic might cause learning difficulties as well as misconcepts in their following learning processes. This study aims to provide elementary teachers a part of pedagogical content knowledge about the properties of arithmetic and to induce some didactical implications for teaching the properties of arithmetic in the elementary school level. To do this, elementary school mathematics textbooks since the period of the first curriculum were analyzed. These results from analysis show which properties of arithmetic have been taught, when they were taught, and how they were taught. Based on them, some didactical implications were suggested for desirable teaching of the properties of arithmetic.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.12
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• pp.2714-2726
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• 1997

In this paper, adaptive symbol changes-based medical image compression method is presented. First, the differenctial image domain is obtained using the differentiation rules or obaptive predictors applied to original mdeical image. Also, the algorithm determines the context associated with the differential image from the domain. Then prediction symbols which are thought tobe the most probable differential image values are maintained at a high value through the adaptive symbol changes procedure based on estimates of the symbols with polarity coincidence between the differential image values to be coded under to context and differential image values in the model template. At the coding step, the differential image values are encoded as "predicted" or "non-predicted" by the binary adaptive arithmetic encoder, where a binary decision tree is employed. The simlation results indicate that the prediction hit ratios of differential image values using the proposed algorithm improve the coding gain by 25% and 23% than arithmetic coder with ISO JPEG lossless predictor and arithmetic coder with differentiation rules or adaptive predictors, respectively. It can be used in compression part of medical PACS because the proposed method allows the encoder be directly applied to the full bit-planes medical image without a decomposition of the full bit-plane into a series of binary bit-planes as well as lower complexity of encoder through using an additions when sub-dividing recursively unit intervals.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.8-15
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• 2009

Side-channel attacks including the differential power analysis attack are often more powerful than classical cryptanalysis and have to be seriously considered by cryptographic algorithm's implementers. Various countermeasures have been proposed against such attacks. In this paper, we deal with the masking method, which is known to be a very effective countermeasure against the differential power analysis attack and propose new gate-level conversion methods between Boolean and arithmetic masks. The new methods require only 6n-5 XOR and 2n-2 AND gates with 3n-2 gate delay for converting n-bit masks. The basic idea of the proposed methods is that the carry and the sum bits in the ripple adder are manipulated in a way that the adversary cannot detect the relation between these bits and the original raw data. Since the proposed methods use only bitwise operations, they are especially useful for DPA-securely implementing cryptographic algorithms in hardware which use both Boolean and arithmetic operations. For example, we applied them to securely implement the block encryption algorithm SEED in hardware and present its detailed implementation result.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.820-822
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• 2005

We have designed a 32-bit microprocessor with fixed point digital signal processing functionality. This processor, combines both general-purpose microprocessor and digital signal processor functionality using the reduced instruction set computer design principles. It has functional units for arithmetic operation, digital signal processing and memory access. They operate in parallel in order to remove stall cycles after DSP or load/store instructions, which usually need one or more issue latency cycles in addition to the first issue cycle. High performance was achieved with these parallel functional units while adopting a sophisticated five-stage pipeline stucture.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.935-938
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• 2003

The performance of elliptic curve based on public key cryptosystems is mainly appointed by the efficiency of the underlying finite field arithmetic. This work describes a finite field multiplier and divider which is implemented using SystemC. Also this present an efficient hardware for performing the elliptic curve point multiplication using the polynomial basis representation. In order to improve the speed of the multiplier with as a little extra hardware as possible, adopted hybrid finite field multiplication and finite field divider.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.81-84
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• 2001

In recent years, the design of CMOS VCO at ever-higher frequencies has gained interest. This paper proposes an arithmetic functionality VCO circuit based on a differential ring oscillator for operating in high frequency. The proposed VCO architecture with half adder is able to produce two times higher frequency with my delay cell than conventional VCO produce double oscillation frequency and power dissipation is 14.59mW.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10a
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• pp.214-216
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• 2003

아날로그 NTSC 비디오 디코더 신호를 디코딩하여 디지털화된 컬러 값을 얻기 위해서는 컬러 버스트 신호를 동기화 해야 한다. 이 버스트 신호를 이용하여 Y. I. O의 값을 분리하기 때문이다. 아날로그 디코더의 경우에는 내부에 버스트 신호와 동기화 한 클럭을 PLL이나 DLL등을 이용하여 발생시켜서 I의 위치를 알아낸다. 비디오 신호 해독을 위한 전용의 PLL을 위해 아날로그 방식의 VLSI설계를 하는 것은 많은 노력이 들어갈 뿐만 아니라 특정 Fab에 종속되어 전체 칩의 이식성을 떨어뜨리게 된다. 본 논문에서는 아날로그 PLL이 없이도 디지털 입력데이터의 산술 연산을 통해서 컬러 버스트 동기화를 검출하는 방법을 제안한다.

• The KIPS Transactions:PartC
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• v.17C no.3
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• pp.233-242
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• 2010

In the recent years, power attacks were widely investigated, and so various countermeasures have been proposed. In the case of block ciphers, masking methods that blind the intermediate results in the algorithm computations(encryption, decryption) are well-known. In case of SEED block cipher, it uses 32 bit arithmetic addition and S-box operations as non-linear operations. Therefore the masking type conversion operations, which require some operating time and memory, are required to satisfy the masking method of all non-linear operations. In this paper, we propose a new masked S-boxes that can minimize the number of the masking type conversion operation. Moreover we construct just one masked S-box table and propose a new formula that can compute the other masked S-box's output by using this S-box table. Therefore the memory requirements for masked S-boxes are reduced to half of the existing masking method's one.

• Proceedings of the KIEE Conference
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• 2008.04a
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• pp.79-80
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• 2008

본 논문은 FPGA 기반에서 실수형 프로세서의 설계 및 구현에 대한 내용과 이를 이용하여 휴머노이드 로봇 팔의 위치제어를 위한 PD 제어기반의 신경회로망 제어기의 구현에 대한 내용이다. 설계된 프로세서는 명령어 기반의 처리를 통해 산술 연산 뿐만 아니라 로봇의 제어에 사용되는 외부 모듈의 사용이 가능하도록 설계하였으며, 신경회로망 구현에 사용되는 지수함수를 효율적으로 근사화하기 위한 Taylor series를 이용한 알고리즘을 하드웨어 레벨에서 구현하였다. 휴머노이드 로봇 팔의 위치 추종을 위해 고전적인 PD 제어기를 설계하고 PD 기반의 신경회로망 제어기를 설계하였다. 로봇 팔의 6축 제어를 위한 신경회로망 제어기에 요구되는 많은 연산을 감당하도록 하기 위해 설계된 프로세서를 통해 정의된 프로그래밍언어로 제어 프로그램을 작성하였다. PD 제어기와 PD 기반의 신경회로망 제어기를 하드웨어에 설계하여 로봇팔의 위치 추종을 실험하였으며 성능을 비교 검증하였다. 프로세서는 Altera의 Stratix II EP2S180 DSP development board에 구현되었으며 실험적으로 25MIPS의 성능을 가지는 것으로 나타났다.