• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.9
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• pp.261-268
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• 2018

The use of electric cable was limited due to the installation time and large space as the increase of power demand and load quantity in side line. In order to solve these problems, the application of busway system which can supply the large current was increasing. But it was lack of methods of performance tests to evaluate the reliability and results of test for busway system. In this paper, we presented items to evaluate the reliability test for epoxy coated busway system with reference to IEC 61349-6. In addition, we proposed items to evaluate the reliability and long term life cycle test for the epoxy coated busway system. The combined acceleration deterioration test that reflects actual conditions of the survey as much as possible was conducted considering both thermal and electrical stresses. The deterioration condition was selected to satisfy fifty years life expectation and the insulation performance verification test of the busway system confirmed the long term life prediction. Furthermore, as test items for reliability assessment of compliance with the environment for the use of temperature, humidity and load current where busway system was installed, thermal overload test, water immersion test, cold shock temperature test and thermal cycle test were performed. And we examined changes in characteristics and abnormality after tests. From results, the test items presented to evaluate performance and reliability of the epoxy insulated busway system were confirmed to be appropriate in this paper, and the performance of the product was also confirmed to be excellent for reliability tests.

• Clean Technology
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• v.26 no.2
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• pp.96-101
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• 2020

In this paper, the commercial feasibility of trigeneration, producing heat, power, and hydrogen (CHHP) and using biogas derived from macroalgae (i.e., seaweed biomass feedstock), are investigated. For this purpose, a commercial scale trigeneration process, consisting of three MW solid oxide fuel cells (SOFCs), gas turbine, and organic Rankine cycle, is designed conceptually and simulated using Aspen plus, a commercial process simulator. To produce hydrogen, a solid oxide fuel cell system is re-designed by the removal of after-burner and the addition of a water-gas shift reactor. The cost of each unit operation equipment in the process is estimated through the calculated heat and mass balances from simulation, with the techno-economic analysis following through. The designed CHHP process produces 2.3 MW of net power and 50 kg hr^-1 of hydrogen with an efficiency of 37% using 2 ton hr^-1 of biogas from 3.47 ton hr^-1 (dry basis) of brown algae as feedstock. Based on these results, a realistic scenario is evaluated economically and the breakeven electricity selling price (BESP) is calculated. The calculated BESP is ¢10.45 kWh^-1, which is comparable to or better than the conventional power generation. This means that the CHHP process based on SOFC can be a viable alternative when the technical targets on SOFC are reached.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.6
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• pp.115-121
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• 2015

In this paper, we proposed an iterative data-flow optimal scheduling algorithm based on genetic algorithm for high-performance multiprocessor. The basic hardware model can be extended to include detailed features of the multiprocessor architecture. This is illustrated by implementing a hardware model that requires routing the data transfers over a communication network with a limited capacity. The scheduling method consists of three layers. In the top layer a genetic algorithm takes care of the optimization. It generates different permutations of operations, that are passed on to the middle layer. The global scheduling makes the main scheduling decisions based on a permutation of operations. Details of the hardware model are not considered in this layer. This is done in the bottom layer by the black-box scheduling. It completes the scheduling of an operation and ensures that the detailed hardware model is obeyed. Both scheduling method can insert cycles in the schedule to ensure that a valid schedule is always found quickly. In order to test the performance of the scheduling method, the results of benchmark of the five filters show that the scheduling method is able to find good quality schedules in reasonable time.

• Journal of the Korean Electrochemical Society
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• v.6 no.3
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• pp.196-202
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• 2003

We investigated the effect of both 4 types additives and $0.5wt\%\;Pb_3O_4$ which have been reported to show an improvement on the performance of Zinc anode. And Experimental methods such as corrosion potential measurement, potentiodynamic polorization test and charging-discharging cycle life test were carried out in $40 wt\%$ KOH with $Pb_3O_4(0.5, \;10\;&\;2.0wt\%)$ and 4 types additives $(0.4wt\%\;of\;Ca(OH)_2$, 0.025M of Citrate, Tartrate and Gluconate). Corrosion potential was shifted to high direction and also changed to high and low direction repeatedly with increasing of $Pb_3O_4$ quantity. However by adding $0.5wt\%\;Pb_3O_4$, corrosion potential shifted to low direction and showed stable condition. Furthermore it was well known that corrosion resistance was predominantly increased compared to no addition and improved charging-discharging property with adding additives. By SEM analysis, it was concluded that the morphology of surface in case of only $0.5wt\%\;Pb_3O_4$ addition was nearly the same as that of Tartrate additive and in the other additives such as $Ca(OH)_2$, Citrate, Tartrate and Gluconate, their morphologies showed dendrite growth. Eventually it was thought that the additive of Tartrate indicated comparatively good corrosion resistance effect as well as charging-discharging property improvement among those four types additives.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.401-404
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• 2015

This paper proposes a high-performance in-loop filter in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. HEVC uses in-loop filter consisting of deblocking filter and SAO(Sample Adaptive Offset) to solve the problems of quantization error which causes image degradation. In the proposed in-loop filter encoder hardware architecture, the deblocking filter and SAO has a 2-level hybrid pipeline structure based on the $32{\times}32CTU$ to reduce the execution time. The deblocking filter is performed by 6-stage pipeline structure, and it supports minimization of memory access and simplification of reference memory structure using proposed efficient filtering order. Also The SAO is implemented by 2-statge pipeline for pixel classification and applying SAO parameters and it uses two three-layered parallel buffers to simplify pixel processing and reduce operation cycle. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 205K logic gates in TSMC 0.13um process. At 110MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 30fps in realtime.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.875-878
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• 2015

In this paper, we propose an intra prediction hardware architecture with less processing time, computations and reduced hardware area for a high performance HEVC encoder. The proposed intra prediction hardware architecture uses common operation units to reduce computational complexity and uses $4{\times}4$ block unit to reduce hardware area. In order to reduce operation time, common operation unit uses one operation unit to generate predicted pixels and filtered pixels in all prediction modes. Intra prediction hardware architecture introduces the $4{\times}4$ PU design processing to reduce the hardware area and uses intemal registers to support $32{\times}32$ PU processmg. The proposed hardware architecture uses ten common operation units which can reduce execution cycles of intra prediction. The proposed Intra prediction hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 41.5k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 150MHz, it can support 4K UHD video encoding at 30fps in real time, and operates at a maximum of 200MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.554-557
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• 2016

Recently, supercomputer has been increasingly adopted as a computing environment for scientific simulation as well as education, healthcare and national defence. Especially, supercomputing system with heterogeneous computing resources is gaining resurgence of interest as a next-generation problem solving environment, allowing theoretical and/or experimental research in various fields to be free of time and spatial limits. However, traditional supercomputing services have only been handled through a simple form of command-line based console, which leads to the critical limit of accessibility and usability of heterogeneous computing resources. To address this problem, in this paper, we provide the design and implementation of web-based HPC (High Performance Computing) job management framework for computational scientific simulation. The proposed framework has highly extensible design principles, providing the abstraction interfaces of job scheduler (as well as bundle scheduler plug-ins for LoadLeveler, Sun Grid Engine, OpenPBS scheduler) in order to easily incorporate the broad spectrum of heterogeneous computing resources such as cluster, computing cloud and grid. We also present the detailed specification of HTTP standard based RESTful endpoints, which manage simulation job's life-cycles such as job creation, submission, control and status monitoring, etc., enabling various 3rd-party applications to be newly created on top of the proposed framework.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.9
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• pp.1916-1932
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• 1997

The synchronous stream cipher which require absoulte clock synchronization has the problem of synchronization loss by cycle slip. Synchronization loss makes the state which sender and receiver can't communicate with each other and it may break the receiving system. To lessen the risk, we usually use a continuous resynchronization method which achieve resynchronization at fixed timesteps by inserting synchronization pattern and session key. While we can get resynchronization effectively by continuous resynchroniation, there are some problems. In this paper, we proposed an adaptive resynchronization algorithm for cipher system using HDLC protocol. It is able to solve the problem of the continuous resynchronization. The proposed adaptive algorithm make resynchronization only in the case that the resynchronization is occurred by analyzing the address field of HDLC. It measures the receiving rate of theaddress field in the decision duration. Because it make resynchronization only when the receiving rate is greateer than the threshold value, it is able to solve the problems of continuous resynchronization method. When the proposed adaptive algorithm is applied to the synchronous stream cipher system in packet netork, it has addvance the result in R_e and D_e.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.436-442
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• 2020

ESS(energy storage system) has recently become an important power source in various areas due to increased renewable energy resources. The more ESS is used, the less the effective capacity of the ESS. Therefore, it is important to manage the remaining useful lifetime(RUL). RUL can be checked regularly by inspectors, but it is common to be monitored and estimated by an automated monitoring system. The accurate state estimation is important to ESS operator for economical and efficient operation. RUL estimation model usually requires complex mathematical calculations consisting of cycle aging and calendar aging that are caused by the operation frequency and over time, respectively. A lightweight RUL estimation model is required to be embedded in low-performance processors that are installed on ESS. In this paper, a lightweight ESS RUL estimation model is proposed to operate on low-performance micro-processors. The simulation results show less than 1% errors compared to the original RUL model case. In addition, a performance analysis is conducted based on ATmega 328. The results show 76.8 to 78.3 % of computational time reduction.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.1
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• pp.369-377
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• 2013

This paper deals with the state of charge(SOC) and life cycle evaluation algorithm for lead-acid battery, which is essential factor of the electric vehicle(EV) and the stabilization of renewable energy in the smart grid. In order to perform the effective operation of the lead-acid battery, SOC and life cycle evaluation algorithm is required. Specific gravity with the change of electrolyte temperature inside battery case should be obtained to evaluate the SOC of lead-acid battery, however it is difficult to measure the electrolyte temperature of sealed type lead-acid battery. To overcome this problem, this paper proposes the equation of thermal transmission to compensate internal temperature of the lead-acid battery. Also, it is difficult to exactly evaluate the life cycle of battery, depending on the operation conditions of lead-acid battery such as charging and discharging state, self discharging rate and environmental issue. In order to solve the problem, this paper presents the concept for gravity accumulation of charge and discharge cycle, which is the value converted at $20^{\circ}C$. By using the proposed algorithm, this paper propose the test device based on the Labview software. The simulation results show that it is a practical tool for the maintenance of lead-acid battery in the field of industry.