• Journal of Korea Multimedia Society
• /
• v.13 no.1
• /
• pp.102-110
• /
• 2010

H.264 SVC(Scalable Video Coding) provides the advantages of low disk storage requirement and high scalability. However, a streaming server or a user terminal has to extract a bit stream from SVC file. This paper proposes a bit stream extraction method which can get the maximum PSNR value while date bit rate does not exceed the available network bandwidth. To do this, this paper obtains the information about extraction points which can get the maximum PSNR value offline and decides the spatial/temporal resolution of a bit stream at run-time. This resolution information along with available network bandwidth is used as the parameters to a bit stream extractor. Through experiment with JSVM reference software, we proved that proposed bit stream extraction method can get a higher PSNR value.

• Proceedings of the Korean Information Science Society Conference
• /
• 2002.10c
• /
• pp.700-702
• /
• 2002

본 논문은 16-비트 고정된 명령어 형식을 갖는 32-비트 EISC(Extendable Instruction Set Computer) 코어 구현에 대하여 기술하였다. EISC구조는 코드 밀도가 높은 확장 오퍼랜드(operand) 형식을 사용하여 메모리 크기를 줄일 수 있으므로 ASIC 구현시 저전력 시스템 및 소형화된 임베디드 시스템을 위한 프로세서 구현을 가능하게 한다. 설계된 프로세서는 AE32000 명령어 셋과 호환이 가능하도록 설계되었으며 5단 파이프라인을 적용하여 프로세서의 성능을 높였다. 또한 BTB(Branch Target Buffer)를 사용하여 분기 지연을 줄여 낮은 CPI(Clock Per Instruction)을 유지하게 하였다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2006.05a
• /
• pp.929-932
• /
• 2006

본 논문에서는 암호화된 Scalable Video Coding (SVC) 비트스트림에서의 조건적 접근제어을 위한 키 관리 기법을 제안한다. 스케일러블 비디오 코딩 기술은 한번 인코딩 후 비트스트림 추출을 통해 다양한 확장성(scalabbility)을 가지는 비디오를 생성 할 수 있는 기술로 확장하는 단위마다 다른 키로 암호화 하여 조건적 접근제어를 구성 할 수 있다. 그러나 기존의 조건적 접근제어 기술은 암호화 시 복수의 키가 필요하며 이는 키의 관리와 분배에 어려움을 준다. 이러한 문제를 해결하기 위해 본 논문에서는 기존의 스케일러블 코딩기법에서 조건적 접근제어를 위한 키 관리기법을 살펴보고 SVC 의 확장 구조에 맞는 키 관리 기법을 제안한다. 제안한 방법은 SVC 를 이용한 스트리밍 테스트베드에서 구현되어, 조건적 접근제어를 위한 키 관리기능의 유용성을 확인하였다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2013.06a
• /
• pp.267-269
• /
• 2013

본 논문은 제한된 1비트 변환 (Constrained One-Bit Transform : C1BT) 알고리즘의 정합 오차 기준의 동적 범위를 확장하는 알고리즘을 제안하였다. C1BT는 정합 오차 기준으로 SAD (Sum of Absolute Differences)를 사용하지 않고 CNNMP (Constrained Number of Non-Matching Points)를 사용하여 하드웨어 구현을 용이하게 하고 속도를 대폭 향상시켰다. 이는 기존의 움직임 예측 방법인 전역 탐색 알고리즘 (Full Search Algorithm: FSA)과 비교하여 연산량을 크게 줄였으나 움직임 예측의 정확도를 현저히 감소시켰다. 이 점을 개선하기 위해 이 논문에서는 C1BT의 정합 오차 기준을 확장하여 움직임 예측의 정확도를 높이는 알고리즘을 제안하였다. 기존의 C1BT와 제안하는 알고리즘을 비교한 결과에서 제안하는 알고리즘이 기존의 C1BT에 비해 움직임 예측의 정확도의 기준인 PSNR 측면에서 더 우수한 성능을 보였다.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.36D no.5
• /
• pp.11-20
• /
• 1999

The data transfer width between the mocroprocessor and the memory comes to a critical part that limits system performance since the data transfer width has been as it was while the performance of a microprocessor is getting higher due to its continuous development in speed. And it is important that the memory should be in small size for the reduction of embedded microprocessor's price which is integrated on a single chip with the memory and IO circuit. In this paper, a mocroprocessor tentatively named as Extendable Instruction Set Computer(EISC) is proposed as the high code density 32 bit mocroprocessor architecture. The 32 bit EISC has 16 general purpose registers and 16 bit fixed length instruction which has the short length offset and small immediate operand. By using and extend register and extend flag, the offset and immediate operand could be extended. The proposed 32 bit EISC is implemented with an FPGA and all of its functions have been tested and verified at 1.8432MHz. And the cross assembler, the cross C/C++ compiler and the instruction simulator of the 32 bit EISC shows 140-220% and 120-140% higher code density than RISC and CISC respectively, which is much higher than any other traditional architectures. As a consequence, the EISC is suitable for the next generation computer architecture since it requires less data transfer width compared to any other ones. And its lower memory requirement will embedded microprocessor more useful.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.17 no.1
• /
• pp.31-40
• /
• 2022

This paper proposes an augmented QSBC(Quantum Short-Block Code) that preserves the function of the existing QSBC and adds a single bit-flip error correction function due to Pauli X and Y errors. The augmented QSBC provides the diagnosis and automatic correction of a single Pauli X error by inserting additional auxiliary qubits and Toffoli gates as many as the number of information words into the existing QSBC. In this paper, the general expansion method of the augmented QSBC using seed vector and the realization method of the Toffoli gate of the single bit-flip error automatic correction function reflecting the scalability are also presented. The augmented QSBC proposed in this paper has a trade-off with a coding rate of at least 1/3 and at most 1/2 due to the insertion of auxiliary qubits.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.49 no.7
• /
• pp.12-22
• /
• 2012

The main drawback of the multi-code spread spectrum communication system, which spreads data bits stream by the multiplexed orthogonal codes, is the need for the highly linear amplifier. Several constant amplitude precoding schemes have been proposed for the Walsh code or the extended $m$-sequence based multi-code spread spectrum systems. In the constant amplitude spread spectrum systems the accompany code is transmitted together with orthogonal codes to maintain the transmitter output in a constant level. In this paper we propose the use of the accompany in the receiver to improve the BER performance. The proposed receiver has the capability to correct the code detection error(up to one code error). We carried out simulations to verify the validity of the proposed algorithm. BER performance improvement was noticed compared with the conventional receiver.

• Superconductivity and Cryogenics
• /
• v.24 no.1
• /
• pp.4-9
• /
• 2022

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.24 no.10B
• /
• pp.1912-1920
• /
• 1999

In this paper, we propose a layered video coding scheme which can generate multi-layered bitstream for heterogeneous environments. A new motion prediction structure with temporal hierarchy of frames is developed to afford temporal resolution scalability and the wavelet decomposition is adopted to offer spatial acalability. The proposed scheme can have a higher compression ratio than replenishment schemes by using motion estimation and compensation which can further reduce the temporal redundancy, and it effectively works with dynamic adaption or errors using dispersive intra-subband update (DISU). Moreover, data rate scalability can be attained by employing embeded zerotree wavelet (EZW) technique which can produce embeded bitstream. Therefore, the proposed scheme is expected to be effectively used in heterogeneous environments such as the Internet, ATM, and mobile networks where interoperability are required.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2017.10a
• /
• pp.569-570
• /
• 2017

Bitcoin-based blockchain technology provides an infrastructure that enables anonymous smart contracts, low-cost remittances, and online payments. However, the block-chain technology that implements the bitcoin has scalability constraints in tradeoffs between throughput and latency. To solve these problems, the Byzantine fault tolerant block-chain technique has been proposed. This technique improves throughput without increasing latency by selecting a leader and constructing many microblocks that do not contain proofs of work within the existing block by the leader. However, this technique may be less secure than existing techniques in selecting the reader. In this paper, we propose a technique for scalability of the blockchain technology by using microblock technology and parallel execution technique. Within one microblock there is information about several transactions. In the proposed scheme, the throughput of the microblocks can be increased by performing concurrently.