• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.786-792
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• 2016

Camellia was jointly developed by Nippon Telegraph and Telephone Corporation and Mitsubishi Electric Corporation in 2000. Camellia specifies the 128-bit message block size and 128-, 192-, and 256-bit key sizes. In this paper, a modified round operation block which unifies a register setting for key schedule and a conventional round operation block is proposed. 16 ROMs needed for key generation and round operation are implemented using only 4 dual-port ROMs. Due to the use of a message buffer, encryption/decryption can be executed without a waiting time immediately after KA and KB are calculated. The suggested block cipher Camellia algorithm is designed using Verilog-HDL, implemented on Virtex4 device and operates at 184.898MHz. The designed cryptographic core has a maximum throughput of 1.183Gbps in 128-bit key mode and that of 876.5Mbps in 192 and 256-bit key modes. The cryptographic core of this paper is applicable to security module of the areas such as smart card, internet banking, e-commerce and satellite broadcasting.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.12
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• pp.648-654
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• 2002

The Virtual Interface Architecture(VIA) is an industry standard for communication over system area networks(SANs). M-VIA is a software implementation of VIA technology on Linux. In this paper, we implemented the M-VIA on an AceNIC Gigabit Ethernet by developing a new AceNIC driver for the M-VIA. We analyzed the M-VIA data segmentation processes. When a Gigabit Ethernet MTU is larger than 1514 bytes, M-VIA data segmentation size leaves much room for improvement. So we experimented with various MTU and M-VIA data segmentation size and compared the performances.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.10a
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• pp.223-225
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• 2021

Modular multiplication is a key operation for point scalar multiplication of ECC, and is the most important factor affecting the performance of ECC processor. This paper describes a design of a 256-bit modular multiplier that adopts 3-way Toom-Cook multiplication algorithm and modified fast reduction algorithm. One 90-bit multiplier and three 264-bit adders were used to optimize the hardware size and the number of clock cycles required. The modular multiplier was verified by implementing it using Zynq UltraScale+ MPSoC device and the modular multiplication operation takes 15 clock cycles.

• Journal of Korea Society of Industrial Information Systems
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• v.16 no.3
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• pp.23-33
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• 2011

In this paper, the wavelet image coder, that can encode the bit-level information of wavelet coefficients, is proposed. The proposed coder is used the modified EZW algorithm and significant coefficient array that has bit level information of the wavelet coefficients to reduce the memory requirement in coding process. The significant coefficient array is two dimensional data structure that has bit level information of the wavelet coefficients. The proposed algorithm performs the coding of the significance coefficients and coding of bit level information of wavelet coefficients at a time by using the significant coefficient array. Experimental results show a better or similar performance of the proposed method when compared with conventional embedded wavelet coding algorithm. Especially, the proposed algorithm performs stably without image distortion at various bit rates with minimum memory usage by using the significant coefficient array.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.9
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• pp.1325-1332
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• 2013

The first frame of a GOP, an I frame, is encoded in intra mode which generates a larger number of bits. In addition, the I frame is used for the inter mode encoding of the following frames. Thus the intial QP for the I frame affects the first frame as well as the following frames. In our previous work, we analyzed the number of bits for an I frame and showed that the ratio of the number of bits which maximizes the PSNR of a GOP maintains similar value regardless of GOP's. In this paper, we propose a R-Q model which can be used for the calculation of the initial QP given the amount of bits for an I frame. The proposed model is simple and adaptively modifies model parameters, so it can be applicable to the real-time application. It is shown by experimental results that the proposed model captures initial QP characteristics effectively and the proposed method for model parameters accurately estimates the real values.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.94-104
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• 2008

In this paper, we propose a new architecture of multiplier-and-accumulator (MAC) for high speed multiplication and accumulation arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator which has the largest delay in MAC was removed and its function was included into CSA, the overall performance becomes to be elevated. The proposed CSA tree uses 1's complement-based radix-2 modified booth algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of operands. The CSA propagates the carries by the least significant bits of the partial products and generates the least significant bits in advance for decreasing the number of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate results in the type of sum and carry bits not the output of the final adder for improving the performance by optimizing the efficiency of pipeline scheme. The proposed architecture was synthesized with $250{\mu}m,\;180{\mu}m,\;130{\mu}m$ and 90nm standard CMOS library after designing it. We analyzed the results such as hardware resource, delay, and pipeline which are based on the theoretical and experimental estimation. We used Sakurai's alpha power low for the delay modeling. The proposed MAC has the superior properties to the standard design in many ways and its performance is twice as much than the previous research in the similar clock frequency.

• Journal of Practical Engineering Education
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• v.11 no.2
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• pp.167-174
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• 2019

In the case of Java programming education for non-major undergraduates, there are no examples of applying the physical computing education method. The advantage of physical computing education is that you can directly check the SW processing output result according to the input value of digital and analog sensor, so that you can quickly correct programming errors and improve learner's learning interest and satisfaction. In this paper, we use the microbits to combine physical computing education with basic Java programming education. In addition, according to the computational thinking process, we proposed an educational method for creating Java programs using microbits. Through block programming to control the microbits, we designed an algorithm and applied a training method to convert it into a Java program. In addition, the results of students' evaluations were analyzed in the course applying the education method, and the effectiveness of the education method using the microbit was analyzed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2C
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• pp.172-181
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• 2010

In this paper, we propose an adaptive block quantization method. The propose method perfrect reconstructs side information without high complexity in the encoder side, as transmitting motion vectors from a decoder to an encoder side. Also, at the encoder side, residual signals between reconstructed side information and original frame are adaptively quantized to minimize parity bits to be transmitted to the decoder. The proposed method can effectively allocate bits based on bit error rate of side information. Also, we can achieved bit-saving by transmission of parity bits based on the error correction ability of the LDPC channel decoder, because we can know bit error rate and positions of error bit in encoder side. Experimental results show that the proposed algorithm achieves bit-saving by around 66% and delay of feedback channel, compared with the convntional algorithm.

• Journal of Korea Society of Industrial Information Systems
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• v.20 no.6
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• pp.21-27
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• 2015

We analyze the problem that is occurring when using parity mode transformation required for 9 bit serial communication under Linux environment and propose the solution. The parity mode change is used for 9 bit serial communication in the Linux that by nature supports only 8 bit serial communication. delay (around OS tick) arises. Our analysis shows that the cause is minimum length of waiting time to transmit data remained in Tx FIFO buffers. A modified Linux serial driver proposed in this paper decreases the delay less than 1ms by using accurate time delaying. Despite various system communication interfaces, enormous existing standards and system have adopted RS-232 serial communication, and the part of them have communicated by 9bit serial.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2006.11a
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• pp.133-136
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• 2006

한정된 네트워크 대역폭을 가진 현재의 인터넷에서 영상의 품질을 향상시키기 위해 영상의 비트율을 높이는 것은 비용 등 여러 가지 문제로 인해 현실적으로 많은 어려움이 있다. 따라서 비록 충분하지 못한 비트율의 영상을 전송받더라도 전송받은 영상의 화질을 높이는 연구가 다양한 방법으로 진행되고 있다. 영상의 화질을 향상시키는 많은 방법 중 후처리 기법은 이러한 잡음을 효과적으로 제거 할 수 있으면서 동영상 압축 표준 복호기를 수정할 필요가 없기 때문에 좋은 해결책이 된다. 동영상의 압축 과정에서 낮은 비트율로 인해 발생하는 화질 열화 현상 중에 쉽게 완화 할 수 있고, 영상의 질이 비용 대비 높은 효율로 좋아지는 대표적인 현상이 블록화 현상이다. 일반적으로 블록화 현상은 영상의 고주파대역에서 나타나므로 본 논문에서 영상의 고주파 성분과 블록화 현상을 구분하기 위해 Sobel 마스크를 사용한다. 구분된 블록화 현상이 발생한 매크로블록의 양쪽 경계면에 4-tap 저주파 통과 필터를 사용하여 블록화 현상을 효과적으로 완화할 수 있다. 개선된 영상의 화질 평가 기법으로 신호처리 분야에서 많이 사용되는 객관적인 지표인 PSNR에 의한 평가와 함께 실제 인간의 시각을 기준으로 주관적이고 감성적인 관찰에 의한 평가를 함께 수행한다.