• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.1
• /
• pp.1-11
• /
• 1999

In this paper, we proposed a design method of parameterized viterbi decoder, which automatically synthsizes the diverse viterbi deciders used in the digital mobile communication systems. It is designed to synthesize a viterbi decoder specified by user-provided parameters. Those parameters are constraint length, code rate generator polynomials of teh convolutional encoder, data rate and bits/frame of the data transmission, and soft decision bits of viterbi decoder. For the design of the parameterized viterbi decoder, we designed a user interface module C-language, and a viterbi decoder module in a hierarchical atructure using VHDL language and its generic statement. For the verification of the parameterized viterbi decoder, we compared our synthesized viterbi decoder with the conventional viterbi decoder which is designed for the IS-95 CDMA system. The proposed design method of the viterbi decoder will be a new method to obtain a required viterbi decoder in a very short time only by supplying the design parameters.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.9 no.3
• /
• pp.587-594
• /
• 2005

In the paper, after we propose a viterbi decoder which has multiple buffering and parallel processing decoding scheme through expanding time-divided imput signal, and map a FPGA, we implement a channel coding system together with PC-based software. Continuous input signal is buffered as order of decoding length and is parallel decoded using a high speed cell for viterbi decoding. Output data rate increases linearly with the cell formed the viterbi decoder, and flexible operation can be satisfied by programming controller and modifying input buffer. The tell for viterbi decoder consists of HD block for calculating hamming distance, CM block for calculating value in each state, TB block for trace-back operation, and LIFO. The implemented cell of viterbi decoder used 351 LAB(Logic Arrary Block) and stably operated in maximum 139MHz in APEX20KC EP20K600CB652-7 FPGA of ALTERA. The whole viterbi decoder including viterbi decoding cells, input/output buffers, and a controller occupied the hardware resource of $23\%$ and has the output data rate of 1Gbps.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.11
• /
• pp.53-61
• /
• 2002

This paper proposes new DSP instructions and their architecture which efficiently implements the Viterbi decoding algorithm. The proposed architecture, supporting typical signal processing functions as in existing DSP chips, consists of an array of operational units and data path structures adequate to the Viterbi algorithm. While existing DSP chips perform Viterbi decoding at the rate of about several dozen kbps, the proposed architecutre can give the rate of 6.25 Mbps on 100 MHz DSP chips, which is nearly the same performance as that of custom-designed Viterbi processors. Therefore, the architecture can meet the standard of IMT-2000 having the 2Mbps data rate.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.6B
• /
• pp.767-775
• /
• 2001

본 논문에서는 비터비 검출기의 복잡도와 전력소모를 감소시킬 수 있는 폴딩 비터비 검출기를 제안하였다. 제안된 폴딩 비터비 검출기는 상태 천이도가 대칭적인 것을 이용하여 상태는 서로 반전된 값을 갖는 것끼리 묶어지며, 확률거리의 경우 서로 부호가 반대인 값끼리 묶여진다. 제안된 폴딩 비터비 검출기를 EPRML 읽기 채널에 적용할 경우 확률거리 계산에 필요한 두 개의 가산기를 하나의 가감산기로 대체하여 기존의 GVA 알고리즘에 비해 하드웨어 복잡도를 37.4% 감소시킬 수 있었다. 또한 불필요한 전력소모의 원인이 되는 글리치 발생을 신호 재배치와 병렬 구조와 같은 상위 수준의 저전력 기법을 적용하여 억제한 결과 12.7%의 전력소모 감소를 나타내었다.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.5 no.1
• /
• pp.61-66
• /
• 2001

In this paper, we design high speed Viterbi decoding algorithm which is aimed for Wireless LAN. Wireless LAN transmits data at rate 6∼54 Mbps. This high speed is not easy to implement Viterbi decoder with single ACS. So parallel ACS butterfly structure is to be used and several time-dependent problem is to be solved. We simulate Viterbi algorithm using new branch metric calculating method to save time, and consider trace back algorithm which is adaptable to high speed Viterbi decoder. With simulated, we determine the structure of Viterbi decoder. This architecture is available to high speed and low power Viterbi decoder.

• Proceedings of the Korea Institute of Convergence Signal Processing
• /
• 2003.06a
• /
• pp.234-237
• /
• 2003

본 논문은 이동 통신 및 IEEE 802.lla WLAN에서 사용하고 있는 컨벌루셔널 부호의 복호기인 비터비 복호기의 SMU(Survivor Metric Unit)의 최적 메모리 제어에 관한 연구이다. 비터비 복호기기 구조는 크게 BMU, ACSU, SMU부로 구성된다. 이때 SMU부는 최적의 경로를 역추적 하여 최종 복호 데이터를 출력해 주는 블록으로, 역추적 길이에 따라 메모리 사용 양과 복호 성능이 좌우된다. 따라서 본 논문에서는 최적 메모리 제어 알고리즘을 제안함으로써 복호 속도의 향상과 메모리 사용 양을 줄이는 방법을 제안한다. 제안 알고리즘의 성능을 검증하기 위해 기존의 비터비 복호기와 역추적 길이에 따른 비터비 복호기의 성능을 실험을 통해 분석함으로써 제안 방법의 객관적인 성능을 분석한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2010.05a
• /
• pp.357-359
• /
• 2010

The Viterbi Decoding is one of the most researched areas of the convolutional decoding methods. In this paper, we use various parameters for the substantial Viterbi decoding and discuss some viterbi decoding methods. And, the viterbi algorithms of the methods, we discuss 'Hard Decision' and 'Soft Decision'. So, we compare differences of two methods about decoding methods, performance. Because of having various parameters and decision methods, we discuss the values of various parameter and decision methods in the Gaussian channel about the viterbi decoding methods.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.2
• /
• pp.78-84
• /
• 2000

The Viterbi decoders can be classified into serial Viterbi decoders and parallel Viterbi decoders. Parallel Viterbi decoders can handle higher data rates than serial Viterbl decoders. This paper designs and implements a fully parallel Viterbi decoder for high speed multimedia communications. For high speed operations, the ACS (Add-Compare-Select) module consisting of 64 PEs (Processing Elements) can compute one stage in a clock. In addition, the systolic away structure with 32 pipeline stages is developed for the TB (traceback) module. The implemented Viterbi decoder can support code rates 1/2, 2/3, 3/4, 5/6 and 7/8 using punctured codes. We have developed Verilog HDL models and performed logic synthesis. The 0.6 ${\mu}{\textrm}{m}$ SAMSUNG KG75000 SOG cell library has been used. The implemented Viterbi decoder has about 100,400 gates, and is running at 70 MHz in the worst case simulation.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.41 no.10
• /
• pp.45-52
• /
• 2004

This Paper presents a modified hard decision Viterbi decoder with an error prediction circuit enhancing performance for the burst error inputs. Viterbi decoder employs the maximum likelihood decoding algorithm which shows excellent error correction capability for the random error inputs. Viterbi decoders, however, suffer poor error correction performance for the burst error inputs under the fading channel. The proposed error prediction algorithm increases error correction capability for the burst errors. The algorithm estimaties the burst error data area using the maximum path metric for the erroneous inputs, It calculates burst error intervals based on increases in the maximum values of a path metric. The proposed decoder keeps a performance the same as the conventional decoders on AWGN channels for the IEEE802.l1a WLAN system. It shows performance inproving 15% on the burst error of multi-path fading channels, widely used in mobile systems.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.12A
• /
• pp.1983-1989
• /
• 2001

A new two-step soft output Viterbi algorithm (SOVA) for turbo decoder is proposed and analyzed in 7his paper. Due to the algebraic structure of the proposed algorithm, slate and branch metrics can be obtained wish parallel processing using matrix arithmetic. As a result, the number of multiplications to calculate state metrics of each stage and total memory size can be decreased tremendously. Therefore, it can be expected that the proposed algebraic two-step SOVA is suitable for applications in which low computational complexity and memory size are essential.