• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.55-67
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• 2010

The electrical properties of a back drilled via-hole (BDH) without the open-stub and the plated through via-hole (PTH) with the open-stub, which is called the conventional structure, in a high-count multi~layered (HCML) printed circuit board (PCB) were investigated for a high-speed digital system, and a selected inner layer to transmit a high-speed signal was farthest away from the side to mount the component. Within 10 GHz of the broadband frequency, a design of experiment (DOE) methodology was carried out with three cause factors of each via-hole structure, which were the distance between the via-holes, the dimensions of drilling pad and the anti-pad in the ground plane, and then the relation between cause and result factors which were the maximum return loss, the half-power frequency, and the minimum insertion loss was analyzed. Subsequently, the empirical formulae resulting in a macro model were extracted and compared with the experiment results. Even, out of the cause range, the calculated results obtained from the macro model can be also matched with the measured results within 5 % of the error.

• Journal of IKEEE
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• v.12 no.3
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• pp.144-150
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• 2008

This paper describes the design of a coplanar-stripline(CPS) antenna without via hole in microstrip patch type for 910MHz RFID tags using the HFSS simulator. In order to obtain the simplified fabrication design of the antenna, we have used only an impedance matching network to match the impedance of a RFID-tag chip to that of the antenna, not using bandpass filter(BPF). In advance of the optimized antenna design, we have obtained and shown a good agreement compared with the published antenna for 5.8GHz in order to verify the simulation parameters in the HFSS. Based on the verified simulation parameters in the HFSS, we have designed and optimized the 910MHz-CPS-type microstrip patch antenna. The designed simulation results of the antenna show that the proposed antenna is very proper for RFID tags with the 910MHz center frequency without via hole in the microstrip patch antenna.

• Proceedings of the KWS Conference
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• 2010.05a
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• pp.75-75
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• 2010

3D 패키징 기술은 전기소자의 소형화, 고용량화, 저전력화, 높은 신뢰성등의 요구와 함께 그 중요성이 대두대고 있다. 이러한 3D 패키징의 연결방법은 와이어 본딩 또는 플립칩등의 기존의 방법에서 TSV(Through Silicon Via)를 이용하여 적층하는 방법이 주목받고 있다. TSV는 기존의 와이어 본딩과 비교하여 고집적도, 빠른 신호전달, 낮은 전력소비 등의 장점을 가지고 있어 많은 연구가 진행되고 있다. TSV의 세부 공정 중 비아필링(Via filling)기술은 I/O수 증가와 미세피치화에 따른 비아(Via) 직경의 감소 및 종횡비(Via Aspect Ratio)증가로 인해 기존 필링 공정으로는 한계가 있다. 기존의 비아 홀(Via hole)에 금속을 필링하기 위한 방법으로 전기도금법이 많이 사용되고 있으나, 전기도금법은 전기도금액 조성, 첨가제의 종류, 전류밀도, 전류모드 등에 따라 결과물에 큰 차이가 발생되어, 최적공정조건의 도출이 어렵다. 또한 20um이하의 비아직경과 높은 종횡비로 인하여 충진시 void형성등의 문제점이 발생하기도 한다. 본 연구에서는 용융솔더와 진공을 이용하여 비아를 필링시켰다. 이 방법은 관통된 비아가 형성된 웨이퍼 양단에 압력차를 주어, 작은 직경을 갖는 비아 홀의 표면장력을 극복하고, 용융상태의 솔더가 관통된 비아 홀 내부로 필링되는 방법이다. 관통 비아홀이 형성 된 웨이퍼 위에 솔더페이스트를 $250^{\circ}C$이상 온도를 가해 용융상태로 만든 후 웨이퍼 하부에 진공을 형성하여 필링하는 방법과 용융솔더를 노즐을 통하여 위쪽으로 유동시켜 그 위에 비아홀이 형성된 웨이퍼를 접촉하고 웨이퍼 상부에 진공을 형성하여 필링하는 방법으로 실험을 각각 실시하였다. 이 때, 웨이퍼 두께는 100um이하이며 홀 직경은 20, 30um, 웨이퍼 상부와 하부의 진공차는 약 0.02~0.08Mpa, 진공 유지시간은 1~3s로 실시하여 최적 조건을 고찰하였다. 각 조건에 따른 필링 후 단면을 전자현미경(FE-SEM)을 통해 관찰하였다. 실험 결과 0.04Mpa 이상에서 1s내의 시간에 모든 비아홀이 기공(Void)없이 완벽하게 필링되는 것을 관찰하였으며 이 결과는 기존의 방법에 비하여 공정시간을 감소시켜 생산성이 대폭 향상 될 수 있는 방법임을 확인하였다.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.05a
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• pp.673-674
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• 2012

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2009.10a
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• pp.187-188
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• 2009

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.06a
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• pp.357-358
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• 2008

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.10a
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• pp.160-163
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• 2002

Micro via hole Fabrication is studied by means of minimizing method to circuit size as many electric products developed to portable and minimize. Most of currently micro via hole fabrication using laser is that fabricate insulator layer using CO2 Laser after Cu layer by etching, or fabricate insulator layer using IR after trepanning Cu by UV. In this paper, it was performed that a metal layer and insulator layer were worked upon only one UV laser, and increase to processing speed by experiment.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2015.05a
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• pp.136-136
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• 2015

2007년 일본에서 지갑전화나 지상파 디지털TV 방송기능을 탑재한 휴대전화개발에 힘을 쏟고 있을 무렵, 해외에서 컴퓨터에 가까운 스마트폰이라는 다기능단말기 개발이 진행되고 있었다. 스마트폰은 젊은이를 중심으로 인기가 높아지고 있다. 휴대전화를 시작으로 정밀전자기기에는 인쇄배선판(이하, PWB: Printed Wiring Board)이 내장되어 있다. PWB는 향후 하이브리드차나 전기자동차의 발전과 함께, 차량탑재 수요도 높아질 것이다. 본고에서는 PWB를 지탱하는 동 도금 Via Hole메움에 대하여 기술하였다.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.4
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• pp.47-56
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• 2015

In this paper, the Thermal behavior and reliability characteristics of carbon CCL (Copper Claded Layer), which can be used as the core of HDI (High Density Interconnection) PCB (Printed Circuit Board) are evaluated through experiments and numerical analysis using CAE (Computer Aided Engineering) software. For the characterization of the carbon CCL, it is compared with the conventional FR-4 core and Heavy Cu core. From research results, the deformation amount of the flexure strength of PCB is the highest with pitch grade carbon and thermal behavior of PCB is lowest as temperature increases. In addition, TC (Thermal Cycling), LLTS (Liquid-to-Liquid Thermal Shock) and Humidity tests have been applied in the PCB with carbon core and the reliability of PCB with carbon core is confirmed through reliability tests. Also, possibility of uneven surface of the via hole and wear of the drill bit due to the carbon fibers are analyzed. surface of the via hole is uniform, the surface of the drill bit is smooth. Therefore, it is proved that the carbon CCL has the drilling workability of the same level as conventional core material.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.3 s.333
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• pp.19-24
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• 2005

This paper presents design simulation, implementation, and measurement of a miniaturized GPS/K-PCS dual-band LTCC chip antenna for mobile communication handsets. The dimension of LTCC chip antenna is $9mm\times15mm\times1.2mm$. The meander type radiating patch for dual-band operation is realized by using via holes with 0.3mm height to connect upper and lower-layer antenna. The lower meander type antenna is to be tuned to the lower frequency (GPS) band. The upper meander antenna with via hole connection is to contribute the higher frequency (K-PCS) band. The resonant frequency and frequency ratio of the proposed antenna can be adjusted by changing the height of via-hole and effective path of meander radiating patch. The electrical characteristics of the meander chip antenna applied to a GPS/K-PCS are suitable for mobile communication application.