• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.15 no.5
• /
• pp.219-224
• /
• 2015

Recently, the multi-core processor architecture is widely used in the digital signal processors for enhancing its performance. Multi-core processors are classified either as symmetric or asymmetric. Asymmetric multi-core processors are known to have higher performance and more efficient than symmetric multi-core processors. In order to study the performance enhancement of asymmetric multi-core digital signal processors over the symmetric ones, the trace-driven simulation has been executed for various asymmetric quad-core, octa-core and hexadeca-core digital signal processors and compared with the symmetric ones of similar hardware budget using UTDSP benchmarks as input.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.16 no.1
• /
• pp.233-238
• /
• 2016

Recently, the multi-core processor architecture is widely adopted in the embedded processors for enhancing its performance. Multi-core processors are classified either as symmetric or asymmetric. Asymmetric multicore processors are known to score higher performance and more efficient than symmetric multi-core processors. In order to study the performance enhancement of asymmetric multi-core embedded processors over the symmetric ones, the trace-driven simulation has been executed for various asymmetric embedded dual-core, quad-core, octa-core and hexadeca-core processors and compared with the symmetric ones of similar hardware budget using MiBench benchmarks as input.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.14 no.3
• /
• pp.163-169
• /
• 2014

Recently, the importance of multicore processor system is growing rapidly. Multicore processors are classified either as symmetric or asymmetric. Asymmetric multicore processors consist of a high performance complex core and number of low performance simple cores, and are known to be more efficient than symmetric multicore processors. Therefore, performance impact on various configurations of asymmetric multi-core processor needs to be studied. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed for different asymmetric quad-core and octa-core processors and compared to the corresponding symmetric ones.

• Journal of Korea Society of Industrial Information Systems
• /
• v.26 no.5
• /
• pp.11-19
• /
• 2021

In this paper, we proposed an asymmetric multi-core processor scheduling scheme which is based on the mileage of each core. We considered a big-LITTLE multi-core processor structure, which consists of low power consuming LITTLE cores with general performance and high power consuming big cores with high performance. If a task needs to be processed, the processor decides a core type (big or LITTLE) to handle the task, and then investigate the core with the shortest mileage among unoccupied cores. Then assigns the task to the core. We developed a mileage-based balancing algorithm for asymmetric multi-core assignment and showed that the proposed scheduling scheme is more cost-effective compared to the traditional scheme from a management perspective. Simulation is also conducted for the purpose of performance evaluation of our proposed algorithm.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.16 no.2
• /
• pp.157-163
• /
• 2016

If trace-driven or execution-driven simulation is used for the performance analysis of asymmetric multi-core processors, excessive time and much disk space are necessary. In this paper, statistical simulations are performed for asymmetric multi-core processors with various hardware configurations. For the experiment, SPEC 2000 benchmark programs are used for profiling and synthesis, which is supplied as input for the simulation of asymmetric multi-core processors. As a result, the performance of asymmetric multi-core processor obtained by statistical simulation is comparable to that of the trace-driven simulation with a tremendous reduction in the simulation time.

• Journal of Korea Society of Industrial Information Systems
• /
• v.27 no.6
• /
• pp.69-75
• /
• 2022

We propose energy-efficient scheduling considering real-time constraints and energy efficiency in smart mobile with heterogeneous multi-core structure. Recently, high-performance applications such as VR, AR, and 3D game require real-time and high-level processings. The big.LITTLE architecture is applied to smart mobiles devices for high performance and high energy efficiency. However, there is a problem that the energy saving effect is reduced because LITTLE cores are not properly utilized. This paper proposes a heterogeneous multi-core assignment technique that improves real-time performance and high energy efficiency with big.LITTLE architecture. Our proposed method optimizes the energy consumption and the execution time by predicting the actual task execution time using SVM (Support Vector Machine). Experiments on an off-the-shelf smartphone show that the proposed method reduces energy consumption while ensuring the similar execution time to legacy schemes.

• Journal of Digital Contents Society
• /
• v.19 no.6
• /
• pp.1219-1224
• /
• 2018

Nowaday, smart mobile devices on Internet of Things are required to process and deliver greate amount of data in real-time. Therefore, heterogeneous mult-core architecture such the big.LITTLE core architecture, which shows high energy conservation while guaranteeing high performance, are widely employed on up to date smart mobile devices. The LITTLE cores should be highly utilized to gain higher energy conservation because LITTLE cores have much higher energy efficiency than big cores. In this paper, we propose a core selection algorithm, which tries to firstly assign a real-time task on a LITTLE core rather a big core while the task can be finished within its own deadline. We also perform simulation as performance evaluation to show that our proposed algorithm shows higher energy conservation while guaranteeing the required performance.