• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.68-77
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• 2003

An improved negative capacitance circuit that cancels out input impedance of a front-end in a bioimpedance measurement and operates stably with a low gain margin has been proposed. Since the proposed circuit comprises wide-band operational amplifiers, selecting operational amplifiers is easy, while an operational amplifier of prefer bandwidth should be chosen to apply conventional circuit. Also, since gain margin can be controlled by a feedback resistor connected serially with a feedback capacitor, gain margin is tuneable with a potentiometer. The input impedance of the proposed circuit is two times larger than that of the conventional circuit and 40-times than that without a negative capacitance circuit. Furthermore, closed-loop phase response of the proposed circuit is better than that of the conventional circuit or without a negative capacitance circuit. Above all, for the proposed circuit, the frequency at which a gain peaking occurs is higher than the frequency at which the loop gain becomes a maximum. Thus, the proposed circuit is not affected by a gain peaking and can be operated with a very low gain margin.

• Journal of the Korean Vacuum Society
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• v.15 no.3
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• pp.294-300
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• 2006

We fabricated the distributed feedback (DFB) InP/InGaAs/InP grating structures on InP (100) substrates by metal-organic chemical vapor deposition, and their structural properties were investigated by atomic force microscopy and scanning electron microscopy. Self-assembled InAs/InAlGaAs quantum dots (QDs) were grown on the InP/InGaAs/InP grating structures by molecular beam epitaxy, and their optical properties were compared with InAs/InAlGaAs QDs without grating structure. The duty of the grating structures was about 30%. The PL peak position of InAs/InAlGaAs QDs grown on the grating structure was 1605 nm, which was red-shifted by 18 nm from that of the InAs/InAlGaAs QDs without grating structure. This indicates that the formation of InAs/InAlGaAs QDs was affected by the existence of the DFB grating structures.

• The KIPS Transactions:PartC
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• v.16C no.3
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• pp.357-362
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• 2009

Summation generator can be easily made as a simple hardware or software and it's period and linear complexity are very high. So it is appropriate to mobile security system for ubiquitous environment. But it showed us the weakness by Golic's correlation attack and Meier's fast correlation attack. In this paper, we proposed a Nonlinear Summation Generator(NSG), which is improved by using LFSR and NFSR(nonlinear feedback shift register), is different from $E_0$ algorithm which use only LFSR in summation generator. It enhanced nonlinearity and is hard to decipher even though the correlation attack or fast correlation attack. We also analyzed the security aspects and the performances for the proposed algorithm.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.12
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• pp.13-19
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• 2008

In this paper, we propose a new CL-OSTBC (Closed Loop Orthogonal Space-Time Block Code) scheme for four transmit antennas and compare the scheme with existing closed loop schemes on the performance of BER (Bit Error Rate). In the proposed scheme, a transmitter receives channel feedback information and combines modulated symbols by the symbol combiner, and transmits the symbols encoded by the space-time block encoder. As a result, the proposed scheme achieves full-rate and maximal channel gains by more efficient utilization of the channel feedback information. Moreover, the scheme can reduce computation complexity by using a linear detector. Simulation results on the BER performance show that the proposed CL-OSTBC scheme outperforms existing CL-OSTBC schemes.

• 제어로봇시스템학회:학술대회논문집
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• 1986.10a
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• pp.503-505
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• 1986

주어진 제어대상 모델에 대하여 제어기를 구성하여 실제로 적용하는 경우 모델의 불일치, 모델링에서 고려하지 않은 외란(disturbance), 측정잡음등에 의하여 성능이 설계시와 달라진다. 실제적용에서도 성능을 계속 유지하기 위하여 제어기는 안정성, 계수변화(parameter variation)에 대한 강인성(robustness), 외란상쇄(disturbance rejection) 및 측정잡음에 둔감함등의 특성을 가져야 한다. 귀환(feedback)을 사용하여 제어기를 구성하는 경우 위의 모든 조건을 만족 시킬 수 없으므로 제어목적에 따라 적당한 조건을 선정하여 중요한 특성을 주로 갖게 한다. 본 논문에서는 쌍동선(small waterplane area twin hull ship-SWATHS)에 대하여 PID, LQ, LQG 제어기를 구성하여 안정성, 계수 변화에 대한 강인성, 외란 상쇄 및 측정잡음의 영향을 비교하였다. 쌍동선의 경우 다른 단동선(mono hull ship)에 비하여 접수면(waterplane)이 적으므로 무게증변을 흡수할 수 있는 복원력이 약하여 적은 외력에도 상하동요(heave)와 종동요(pitch)가 심하게 일어난다. 이러한 동요를 줄이는 것이 쌍동선의 제어목적이다. 본 연구에서는 먼저 선형화된 수직축 운동방정식을 이용하여 선체운동의 모델을 구했으며 중첩의 원리(super-position theorem)에 의하여 주파수 응답의 합으로 파도입력을 모델링 하였으며 제어를 위하여 필요한 측정치는 IMU(Inertial Measurement Unit)에서 제공된다고 가정하였다. 쌍동선의 동요의 원인은 파도, 바람, 조류 등이 있으나 파도에 의한 영향이 가장 크므로 본 논문에서는 파도에 의한 영향만을 고려하였다. 파도는 쌍동선에 외란으로 작용하며 측정할 수 없는 양이므로 PID, LQ 제어에서는 제어모델에 포함되지 않지만 LQG 제어에서는 제어모델에 포함된다. LQG 제어의 경우 제어모델에 파도를 백색잡음으로 가정하고 제어기를 구성한 것 (LQG1)과 2차의 쉐이핑필터(shaping filter)를 사용하여 구성한 것(LQG2)으로 나누었다.

• Journal of the Institute of Convergence Signal Processing
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• v.3 no.2
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• pp.53-57
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• 2002

Recently, digital communication system becomes high speed, as communication demand dose not only increases sharply, but an image, voice various kinds data also comes multimedia. In transmitting data at a high speed, the main problem is fading by multipath. A linear or nonlinear distortion arise In multipath channel fading from ISI(Intersymbol Interference). For restoring this distorted signal, A lot of equalizer and adaptive algorithm is introduced. This paper compares and analysises, for improving communication quality in channel which is long delay spread, performance of decision feedback equalizer by RLS algorithm, a channel estimation by RLS-MLSE and viterbi equalizer Particularly, there Is exactly channel estimation of impluse response and excellent property of equalization about channel, which delay spread is long impluse response comparatively and is property of non-minimun phase.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.465-469
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer (PADFE) using a 0.25-${\mu}{\textrm}{m}$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stage are inserted into the critical path of the ADFE by using delayed least-mean-square (DLMS) algorithm Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The singl-chip PADFE contains about 205,000 transistors on an area of about 1.96$\times$1.35-$\textrm{mm}^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.60-69
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer(PADFE) using a 0.25-${\mu}m$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stages are inserted into the critical path of the ADFE by using delayed least-mean-square(DLMS) algorithm. Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width, and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The single-chip PADFE contains about 205,000 transistors on an area of about $1.96\times1.35-mm^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW. Test results show that the fabricated chip works functionally well.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.16 no.3
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• pp.110-115
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• 2002

This paper proposes the adaptive fuzzy control system using the microprocessesor for high precision control of automation systems which exist non-linearities such as saturation, relays, hysteresis, and dead zones. The proposed system which provides the improvement in terms of the control region in transient and adaptive control, first used the frequence-locked mothed driving a system to generate a output voltage proportional to the frequency diffierence of relnence input signal and feedback signal for fast transient response,, and when the error reaches the preset value, used the adaptive fuzzy logic for precision control. The theoretical and experimental studies have been carried out. The presented results from the above investigation show considerable improved performance in the precision control of servo control systems.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.2
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• pp.179-184
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• 2016

The electrical load testing system developed from this study was designed to control rated-capacity-testing or variable-load-testing in an active and precise manner and save electric energy during testing, and also to convert the saved electric energy through the electrical load testing system to grid line. As for the device under testing, it was designed to be applied to not only transformer, rectifier, voltage regulator, inverter which require grid voltage source but, also applied to electric power, aerogenerator, photovoltaic, hybrid generator, battery, etc. which do not require grid voltage source. The system was designed to return the power consumed during the testing to the grid line by connecting the synchronizing pwm inverter circuit to the grid voltage source, and was also made to enable the being-tested system from disuse of approximately 93.4% energy when compared to the conventional load testing system which has used the passive resistor.