• The KIPS Transactions:PartD
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• v.14D no.6
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• pp.675-688
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• 2007

Memory access errors are frequently occurred in C programs. A number of tools and research works have been trying to detect the errors automatically. However, they have one or more of the following problems: inability to detect all memory errors, changing the memory allocation mechanism, incompatibility with libraries, and excessive performance overhead. In this paper, we suggest a new method to solve these problems, and then present a result of comparison to the previous research works through the experiments. Our approach consists of two phases. First is to transform source code at compile time through inserting instrumentation into the source code. And second is to detect memory errors at run time with a bitmap that maintains information about memory allocation. Our approach has improved the error detection abilities against the binary code analysis based ones by using the source code analysis technique, and enhanced performance in terms of both space and time, too. In addition, our approach has no problem with respect to compatibility with shared libraries as well as does not need to modify memory allocation mechanism.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.201-208
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• 2012

In this paper, the hardware design of rate control for real-time video encoded is proposed. In the proposed method, a quadratic rate distortion model with high-computational complexity is not used when quantization parameter values are being decided. Instead, for low-computational complexity, average complexity weight values of frames are used to calculate QP. For high speed and low computational prediction, the MAD is predicted based on the coded basic unit, using spacial and temporal correlation in sequences. The rate control is designed with the hardware for fast QP decision. In the proposed method, a quadratic rate distortion model with high-computational complexity is not used when quantization parameter values are being decided. Instead, for low-computational complexity, average complexity weight values of frames are used to calculate QP. In addition, the rate control is designed with the hardware for fast QP decision. The execution cycle and gate count of the proposed architecture were reduced about 65% and 85% respectively compared with those of previous architecture. The proposed RC was implemented using Verilog HDL and synthesized with UMC $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count of the architecture is about 19.1k with 108MHz clock frequency.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.17-28
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• 1999

In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.

• Journal of KIISE
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• v.45 no.1
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• pp.53-60
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• 2018

This study describes a spatial web object retrieval system using Spark, an in - memory based distributed processing system. Development of social networks has created massive amounts of spatial web objects, and retrieval and analysis of data is difficult by using exist spatial web object retrieval systems. Recently, development of distributed processing systems supports the ability to analyze and retrieve large amounts of data quickly. Therefore, a method is promoted to search a large-capacity spatial web object by using the distributed processing system. Data is processed in block units, and one of these blocks is converted to RDD and processed in Spark. Regarding the discussed method, we propose a system in which each RDD consists of spatial web object index for the included data, dividing the entire spatial region into non-overlapping spatial regions, and allocating one divided region to one RDD. We propose a system that can efficiently use the distributed processing system by dividing space and increasing efficiency of searching the divided space. Additionally by comparing QP-tree with R-tree, we confirm that the proposed system is better for searching the spatial web objects; QP-tree builds index with both spatial and words information while R-tree build index only with spatial information.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1107-1114
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• 2004

System Packet Interface Level 4 Phase 2(SPI-4.2) is an interface for packet and cell transfer between a physical layer(PHY) device and a link layer device, for aggregate bandwidths of OC-192 ATM and Packet Over Sonet/SDH(POS), as well as 10Gbps Ethernet applications. SPI-4.2 core consists of Tx and Rx modules and supports full duplex communication. Tx module of SPI-4.2 core writes 64-bit data word and 14-bit header information from the user interface into asynchronous FIFO and transmits DDR(Double Data Rate) data over PL4 interface. Rx module of SPI-4.2 core operates in vice versa. Tx and Rx modules of SPI-4.2 core are designed to support maximum 256-channel and control the bandwidth allocation by configuring the calendar memory. Automatic DIP4 and DIP-2 parity generation and checking are implemented within the designed core. The designed core uses Xilinx ISE 5.li tool and is described in VHDL Language and is simulated by Model_SIM 5.6a. The designed core operates at 720Mbps data rate per line, which provides an aggregate bandwidth of 11.52Gbps. SPI-4.2 interface core is suited for line cards in gigabit/terabit routers, and optical cross-connect switches, and SONET/SDH-based transmission systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.12A
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• pp.1006-1013
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• 2009

This paper proposes a data stream allocation technique for fair capacity performance in multiuser multiple-input multiple-output (MIMO) systems using block diagonalization (BD) algorithm. Conventional studies have been focused on maximum sum capacity. Thus, there is a very large difference of capacity among users, since user capacity unfairly distributed according to each user channel environment. In additional, poor channel user has very small capacity, since base station allocates the power by using water-filling technique. Also, almost studies limited itself to obtain the additional gain by using the same number of data streams for all users. In this paper, we propose the technique for maximizing sum capacity under the fair performance constraint by allocating data stream according to user channel environment. Also, proposed algorithm has more gain of sum capacity and transmit power than conventional equal allocation via computer simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.10C
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• pp.787-797
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• 2008

In this paper, we propose a fast disparity estimation method considering temporal and spatial redundancy based on a dynamic programming for stereo matching. For the first step, the dynamic programming is performed to estimate disparity vectors with correlation between neighboring pixels in an image. Next, we efficiently compensate regions, which disparity vectors are not allocated, with neighboring disparity vectors assuming that disparity vectors in same object are quite similar. Moreover, in case of video sequence, we can decrease a complexity with temporal redundancy between neighboring frames. For performance comparison, we generate an intermediate-view image using the estimated disparity vector. Test results show that the proposed algorithm gives $0.8{\sim}2.4dB$-increased PSNR(peak signal to noise ratio) compared to a conventional block matching algorithm, and the proposed algorithm also gives approximately 0.1dB-increased PSNR and $48{\sim}68%$-lower complexity compared to the disparity estimation method based on general dynamic programming.

• The Journal of the Korea Contents Association
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• v.9 no.7
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• pp.57-66
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• 2009

Zigbee is a universal communication standard used in USN and is utilized in various applications. Zigbee protocol provides an address within a single PAN network, and at this time, it uses DAA. This is a method that divides a 16-bit address area into blocks with a fixed size according to the depth to assign one to each node. However, this method is limited because it has to assign addresses in 16 bits. As the depth increases, the number of nodes also increases exponentially to the maximal number of routers provided to each depth. Therefore, it is difficult to construct a huge network with numerous routers and large depth as in the places which are wide or have many shadow areas. Besides, since all the operations are performed in a single PAN network, it is hard to make several PANs into a single network. This article suggests new addressing and routing methods that can construct several PAN networks into a single network and combine broad area with less limitation in the number of routers and depth by extending the Zigbee-based network. Moreover, this paper has tested its performance and has verified its usability through substantive tests.

• Journal of KIISE:Software and Applications
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• v.32 no.8
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• pp.819-833
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• 2005

Code size reduction is ever becoming more important for compilers targeting embedded processors because these processors are often severely limited by storage constraints and thus the reduced code size can have a positively significant Impact on their performance. Various code size reduction techniques have different motivations and a variety of application contexts utilizing special hardware features of their target processors. In this work, we propose a novel technique that fully utilizes a set of hardware instructions, called the multiple load/store (MLS), that are specially featured for reducing code size by minimizing the number of memory operations in the code. To take advantage of this feature, many microprocessors support the MLS instructions, whereas no existing compilers fully exploit the potential benefit of these instructions but only use them for some limited cases. This is mainly because optimizing memory accesses with MLS instructions for general cases is an NP-hard problem that necessitates complex assignments of registers and memory off-sets for variables in a stack frame. Our technique uses a couple of heuristics to efficiently handle this problem in a polynomial time bound.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.5A
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• pp.493-500
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• 2006

This paper presents the efficient structure and parameter optimization of downlink beamforming transmitter in OFDMA/TDD system. To design downlink beamforming transmitter for multiple transmit antennas, an efficient beamforming structure for multiple users and the choice of word-length of each block are critical in the aspect of its performance and hardware complexity. We propose an efficient beamforming scheme, which stores the weights of subcarriers into memory without user identification at the receiver of base station and calculates the weights for corresponding user in a subcarrier unit of IFFT input at high speed. Also, we obtain the word-length of main data path and other design parameters by fixed-point simulation analysis. The proposed architecture could reduce the memory size proportional to the maximum number of users per frame, and the processing time of an OFDM symbol at the receiver of base station without the need of additional processing time for calculating the weights at the transmitter.