• Journal of the Korea Computer Industry Society
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• v.10 no.4
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• pp.167-176
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• 2009

In this paper, we propose an improved SHACAL-1 of the same encryption and decryption with a simple symmetric layer. SHACAL-1 has 4 rounds, and each round has 20 steps. Decryption is becoming inverse function of encryption, In this paper, we proposed SHACAL-1 are composed of the first half, symmetry layer and the last half. The first half with SHACAL-1 encryption algorithm 1 round does with 10 steps and composes of 4 round. The last half identically with SHACAL-1 decryption algorithm, has a structure. On the center inserts a symmetry layer, encryption and decryption algorithm identically, composes. In the experiments, the proposed SHACAL-1 algorithm showed similar execution time to that of the SHACAL-1. Thanks to the symmetric layer, the proposed algorithm makes it difficult for the attacks which take advantages of high probability path such as the linear cryptanalysis, differential cryptanalysis. The proposed algorithm can be applicable to the other block cipher algorithms which have different encryption and decryption and useful for designing a new block cipher algorithm.

• Electronics and Telecommunications Trends
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• v.32 no.1
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• pp.72-81
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• 2017

2008년, Satoshi Nakamoto라는 가명을 쓰는 신원미상의 사람(들) 혹은 단체가 비트코인을 소개하였다. 그 이후, 현재 비트코인의 총액은 10억달러 이상에 달한다. 비트코인을 지탱하는 기술인 블록체인에 의해 이론적으로 비트코인은 거의 조작이 불가능하며 거의 영구적으로 기록에 남게 된다. 이 획기적인 기술로 인해 비트코인 이 후 약 700개가 넘는 암호화폐가 생겨났으며, 암호화폐뿐만이 아닌 금융권/비금융권, 정부기관 등 많은 도메인에서 블록체인 기술이 도입되어 가고 있다. 비트코인 이후 가장 대표적인 블록체인 기반의 프로젝트로는 튜링 완전한 컴퓨팅 기능이 있는 이더리움이 있다. 이 튜링 완전한 컴퓨팅 기능으로 인해 이더리움 상에서 투명하게 데이터 저장 및 프로그램 실행을 할 수 있다. 이로 인해 이더리움을 이용한 많은 혁신적인 이용 사례가 생겨났다. 본고에서는 비트코인 후 블록체인의 기술을 이더리움 중심으로 소개하며 해결해야 할 기술적 이슈들과 동향에 관해 분석한다. 그리고 현재 이더리움 외에 개발되어오는 블록체인에 대해 간략히 살펴본다.

• Proceedings of the Korea Information Processing Society Conference
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• 2019.05a
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• pp.201-203
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• 2019

블록체인은 P2P 네트워크로 탈중앙화된 신뢰성 기반 데이터 공유 서비스를 제공한다. 다양한 블록체인 플랫폼 중에서도 이더리움은 가장 상용화된 플랫폼으로 비트코인의 한계를 극복하면서도 스마트 컨트랙트를 통한 신뢰성 있는 서비스를 제공한다. 본 논문에서는 블록체인 기반 분산 컴퓨팅 플랫폼인 이더리움에 속성기반 암호기법을 적용하여 네트워크 내의 블록체인에 대한 제한적 접근 서비스를 제안하고 이를 통해 블록체인 서비스 유형을 제시한다.

• Smart Media Journal
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• v.12 no.9
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• pp.9-18
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• 2023

Black box cryptography is a cryptographic scheme based on a hardware encryption device, operating under the assumption that the device and the user can be trusted. However, with the increasing use of cryptographic algorithms on unreliable open platforms, the threats to black box cryptography systems have become even more significant. As a consequence, white box cryptography have been proposed to securely operate cryptographic algorithms on open platforms by hiding encryption keys during the encryption process, making it difficult for attackers to extract the keys. However, unlike traditional cryptography, white box-based encryption lacks established specifications, making challenging verify its structural security. To promote the safer utilization of white box cryptography, CHES organizes The WhibOx Contest periodically, which conducts safety analyses of various white box cryptographic techniques. Among these, the Differential Computation Analysis (DCA) attack proposed by Bos in 2016 is widely utilized in safety analyses and represents a powerful attack technique against robust white box block ciphers. Therefore, this paper analyzes the research trends in white box block ciphers and provides a summary of DCA attacks and relevant countermeasures. adhering to the format of a research paper.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.401-403
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• 2015

This paper describes an efficient hardware design of 128-bit block cipher algorithm LEA(lightweight encryption algorithm). In order to achieve area-efficient and low-power implementation, round block and key scheduler block are optimized to share hardware resources for encryption and decryption. The key scheduler register is modified to reduce clock cycles required for key scheduling, which results in improved encryption/decryption performance. FPGA synthesis results of the LEA processor show that it has 2,364 slices, and the estimated performance for the master key of 128/192/256-bit at 113 MHz clock frequency is about 181/162/109 Mbps, respectively.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.24 no.4
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• pp.585-592
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• 2014

In this paper, we study the LEA[1] block cipher system in UICC-16bit only. Also, we explain a key-schedule function and encryption/decryption structures, propose an advanced modified key-scheduling, and perform LEA in UICC-16bit that we proposed advanced modified key-scheduling. Also, we compare LEA with ARIA that proposed domestic standard block cipher, and we evaluate the efficiency on the LEA algorithm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.777-779
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• 2014

The LEA(Lightweight Encryption Algorithm) is a 128-bit high-speed/lightweight block cipher algorithm developed by National Security Research Institute(NSRI) in 2012. The LEA encrypts plain text of 128-bit using cipher key of 128/192/256-bit, and produces cipher text of 128-bit, and vice versa. To reduce hardware complexity, we propose an efficient architecture which shares hardware resources for encryption and decryption in round transformation block. Hardware sharing technique for key scheduler was also devised to achieve area-efficient and low-power implementation. The designed LEA cryptographic processor was verified by using FPGA implementation.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.23 no.1
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• pp.11-18
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• 2013

In order to prevent tampering and reverse engineering of executive code, this paper propose a new tamper resistant software mechanism. This paper presents a cryptographic MAC function and a relationship which has its security level derived by the importance of code block instead of by merely getting the encryption and decryption key from the previous block. In this paper, we propose a cryptographic MAC function which generates a dynamic MAC function key instead of the hash function as written in many other papers. In addition, we also propose a relationships having high, medium and low security levels. If any block is determined to have a high security level then that block will be encrypted by the key generated by the related medium security level block. The low security block will be untouched due to efficiency considerations. The MAC function having this dynamic key and block relationship will make analyzing executive code more difficult.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.30 no.1
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• pp.87-100
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• 2020

Researches on Post-quantum blockchain, which is a synthesis of blockchain and post-quantum cryptography[1], are relatively unrevealed areas but have needs to be studied with the regard to the quantum computers. However there could be several fundamental problems, e.g. unsustainably large size of public key and signature, or too lengthy time for sign and verification, if any post-quantum cryptography is adopted to the existing blockchain to implement post-quantum blockchain. Thus, a new method was proposed in this paper that produces fixed length of references for massive signatures and corresponding public keys to enable relatively lightweight transactions. This paper proposed the mechanism that included a new transaction structure and protocols, and demonstrated a post-quantum blockchain that the proposed mechanism was adopted. Through this research, it could enhance compatibility of blockchain regarding post-quantum digital signature, possibly reducing weights of the whole blockchain.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2517-2524
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• 2012

This paper describes an efficient implementation of KS(Korea Standards) block cipher algorithm ARIA. The ARIA crypto-processor supports three master key lengths of 128/192/256-bit and four modes of operation including ECB, CBC, OFB and CTR. A hardware sharing technique, which shares round function in encryption/decryption with key initialization, is employed to reduce hardware complexity. It reduces about 20% of gate counts when compared with straightforward implementation. The ARIA crypto-processor is verified by FPGA implementation, and synthesized with a $0.13-{\mu}m$ CMOS cell library. It has 46,100 gates on an area of $684-{\mu}m{\times}684-{\mu}m$ and the estimated throughput is about 1.28 Gbps at 200 MHz@1.2V.