• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.6
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• pp.93-99
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• 2017

In this research the TOF (time of flight) of ultrasonic signal is measured using Xilinx's Zynq SoC (system on chip). The TOF is calculated from the difference between periods during which RF (radio frequency) and ultrasonic signals come across a distance, and then travelling distance is obtained by multiplying the TOF by the ultrasonic speed in the air. For this purpose, a ultrasonic pulse is generated from a Zynq's internal ADC, a FIR (finite impulse response) filter, and a Kalman filter. And a RF reference pulse is generated from a RF interface. Based on baremetal multiprocessing, the Kalman filter and the RF interface are c-programmed on Zynq's dual processor cores, with other components fabricated on Zynq's FPGA. With this HW/SW co-design, both lower resource utilization and much smaller designing period were obtained than the HW design. As a design tool, Vivado IDE(integrated design environment) is used to design the whole signal processing system in hierarchical block diagrams.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.447-458
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• 2003

A high speed multiplier is essential basic building block for digital signal processors today. Typically iterative algorithms in Signal processing applications are realized which need a large number of multiply, add and accumulate operations. This paper describes a macro block of a parallel structured multiplier which has adopted a 32$\times$32-b regularly structured tree (RST). To improve the speed of the tree part, modified partial product generation method has been devised at architecture level. This reduces the 4 levels of compression stage to 3 levels, and propagation delay in Wallace tree structure by utilizing 4-2 compressor as well. Furthermore, this enables tree part to be combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, multiplier architecture can be regularly laid out with same modules composed of Booth selectors, compressors and Modified Partial Product Generators (MPPG). At the circuit level new Booth selector with less transistors and encoder are proposed. The reduction in the number of transistors in Booth selector has a greater impact on the total transistor count. The transistor count of designed selector is 9 using PTL(Pass Transistor Logic). This reduces the transistor count by 50% as compared with that of the conventional one. The designed multiplier in 0.25${\mu}{\textrm}{m}$ technology, 2.5V, 1-poly and 5-metal CMOS process is simulated by Hspice and Epic. Delay is 4.2㎱ and average power consumes 1.81㎽/MHz. This result is far better than conventional multiplier with equal or better than the best one published.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.3
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• pp.189-199
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• 2009

The amount of information on the Web is explosively growing as the Internet gains in popularity. However, only a small portion of the information on the Web is truly relevant or useful to the user. Thus, offering suitable information according to user demand is an important subject in information retrieval. In e-commerce, the recommender system is essential to revitalize commercial transactions, raise user satisfaction and loyalty towards the information provider. The existing recommender systems are mostly based on user data collected at servers, so user data are dispersed over several servers. Therefore, web servers that lack sufficient user behavior data cannot easily infer user preferences. Also, if the user visits the server infrequently, it may be hard to reflect the dynamically changing user's interest. This paper proposes a novel personalization system analyzing the user preference based on web documents that are accessed by the user on a user device. The system also identifies non-content blocks appearing repeatedly in the dynamically generated web documents, and adds weight to the keywords extracted from the hyperlink sentence selected by the user. Therefore, the system establishes at an early stage recommendation strategies for the web server that has little user data. Also, user profiles are generated rapidly and more accurately by identifying the information blocks. In order to evaluate the proposed system, this study collected web data and purchase history from users who have current purchase activity. Then, we computed the similarity between purchase data and the user profile. We confirm the accuracy of the generated user profile since the web page containing the purchased item has higher correlation than other item pages.

• Journal of Broadcast Engineering
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• v.22 no.3
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• pp.327-338
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• 2017

Exposure fusion is a typical image fusion technique to generate a high dynamic range image by combining two or more different exposure images. In this paper, we propose block-based exposure adjustment considering unique characteristics of human visual system and improved saturation measure to get weight map. Proposed exposure adjustment artificially corrects intensity values of each input images considering human visual system, efficiently preserving details in the result image of exposure fusion. The improved saturation measure is used to make a weight map that effectively reflects the saturation region in the input images. We show the superiority of the proposed algorithm through subjective image quality, MEF-SSIM, and execution time comparison with the conventional exposure fusion algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.8
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• pp.1741-1748
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• 2005

In this paper, we describe VLSI design and performance evaluation of OCB-AES crytographic algorithm that simulataneously provides privacy and authenticity. The OCB-AES crytographic algorithm sovles the problems such as long operation time and large hardware of conventional crytographic system, because the conventional system must implement the privancy and authenticity sequentially with seqarated algorithms and hardware. The OCB-AES processor with area-efficient modular offset generator and tag generator is designed using IDEC Samsung 0.35um standard cell library and consists of about 55,700 gates. Its cipher rate is about 930Mbps and the number of clock cycles needed to generate the 128-bit tags for authenticity and integrity is (m+2)${\times}$(Nr+1), where m and Nr represent the number of block for message and number of rounds for AES encryption, respectively. The OCB-AES processor can be applicable to soft cryptographic IP of IEEE 802.11i wireless LAN and Mobile SoC.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.9
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• pp.16-23
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• 2009

In this paper, we propose a new distributed Alamouti space-time block coding scheme using cooperative relay system composed of one source node, three relay nodes and one destination node. The source node is assumed to be equipped with two antennas which respectively use a 2-beam array to communicate with two nodes selected from the three relay nodes. During the first time slot, the two signals which respectively were transmitted by one antenna at the source, are selected by one relay node, added, amplified, and forwarded to the destination. During the second time slot, the other two relay nodes implement the conjugate and minusconjugate operations to the two received signals, respectively, each in turn is amplified and forwarded to the destination node. This transmission scheme represents a new distributed Alamouti space-time block code that can be constructed at the relay-destination channel. Through an equivalent matrix expression of symbols, we analyze the performance of this proposed space-time block code in terms of the chernoff upper bound pairwise error probability (PEP). In addition, we evaluate the effect of the coefficient $\alpha$ ($0{\leq}{\alpha}{\leq}1$) determined by power allocation between the two antennas at the source on the received signal performance. Through computer simulation, we show that the received signals at the three relays have same variance only when the value of $\alpha$ is equal to $\frac{2}{3}$, as a consequence, a better performance is obtained at the destination. These analysis results show that the proposed scheme outperforms conventional proposed schemes in terms of diversity gain, PEP and the complexity of relay nodes.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2006.11a
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• pp.55-58
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• 2006

차세대 방송서비스 개발의 일환으로 관심을 모으고 있는 다시점 비디오 부호화(multi-view video coding, MVC) 방식은 인접한 여러 대의 카메라로 동시에 획득한 영상을 효과적으로 압축하는데 그 목적이 있다. 이때, 중간시전 영상을 생성하여 부호화하는 과정의 참조영상으로 이용할 수 있으며, 이를 위해서는 다시점 비디오 특성에 맞는 영상보간 방법이 필요하다. 기존에 제안되었던 영상보간법은 변위의 검색범위를 초기에 설정하여 블록정합을 이용하여 화소 단위로 변위를 측정하기 때문에 카메라 사이의 거리가 크거나 객체의 움직임이 커서 변위의 변동이 심한 영상에서는 안정적인 화질의 영상을 얻기 어렵다. 또한, 고정된 크기의 블록을 이용하여 전체 변위를 측정하므로 객체의 변위차가 큰 영역에서 변위 오류가 많이 발생한다. 본 논문에서는 이와 같은 문제를 해결하여 보다 개선된 화질의 중간시점 영상을 얻기 위한 새로운 영상보간법을 제안한다. 영역분할을 이용한 초기의 변위측정 과정에서, 처음부터 최대 변위의 범위를 설정하는 대신에 블록 단위로 대략적인 변위륵 측정한 후에, 가변 블록을 이용하여 보다 세밀한 변위를 측정한다. 이 방법은 변위차가 큰 객체의 경계 부분에서 보다 정확하게 변위를 측정 할 수 있으므로, 화소 단위로 변위를 측정할 때 이전에 추한 변위 정보를 바탕으로 각 화소별로 검색 범위를 설정한다. 적응적으로 설정된 검색 범위를 이용하여 화소 단위의 변위를 측정하면 보다 개선된 변위를 얻을 수 있다. 추가적으로, 변위측정 과정에서 발생하는 변위의 오류를 최대한 줄이기 위해 각 단계별로 미디언 필터를 이용하여 변위 오류를 수정하였다. 본 논문에서 제안한 방법으로 실험한 결과 기존의 영상보간 방법보다 화질이 약 $1{\sim}4dB$ 정도 개선되었다.필, 투명도 등을 위성원격탐사 자료와 GIS를 이용하여 공간분석을 실시하고, 공간분포도를 작성함으로써 대상해역의 해양환경을 파악하였다. 본 연구결과, 분석된 위성자료가 현장조사에 의한 검증이 이루어지지 않을 경우, 영상자료분석을 통한 표층수온 추출은 대기 중의 수증기와 에어로졸에 의한 계산치의 오차가 반영되기 때문에 실측치 보다 낮게 평가 될 수 있으므로, 반드시 이에 대한 검증이 필요함을 알 수 있었다. 현지관측에 비해 막대한 비용과 시간을 절약할 수 있는 위성영상해석방법을 이용한 방법은 해양수질파악이 가능할 것으로 판단되며, GIS를 이용하여 다양하고 복잡한 자료를 데이터베이스화함으로써 가시화하고, 이를 기초로 공간분석을 실시함으로써 환경요소별 공간분포에 대한 파악을 통해 수치모형실험을 이용한 각종 환경영향의 평가 및 예측을 위한 기초자료로 이용이 가능할 것으로 사료된다.염총량관리 기본계획 시 구축된 모형 매개변수를 바탕으로 분석을 수행하였다. 일차오차분석을 이용하여 수리매개변수와 수질매개변수의 수질항목별 상대적 기여도를 파악해 본 결과, 수리매개변수는 DO, BOD, 유기질소, 유기인 모든 항목에 일정 정도의 상대적 기여도를 가지고 있는 것을 알 수 있었다. 이로부터 수질 모형의 적용 시 수리 매개변수 또한 수질 매개변수의 추정 시와 같이 보다 세심한 주의를 기울여 추정할 필요가 있을 것으로 판단된다.변화와 기흉 발생과의 인과관계를 확인하고 좀 더 구체화하기 위한 연구가 필요할 것이다.게 이루어질 수 있을 것으로 기대된다.는 초과수익률이 상승하지만, 이후로는 감소하므로, 반전거래전략을 활용하는 경우 주식투자기간은 24개월이하의 중단기가 적합함을 발견하였다. 이상의 행태적 측면과 투자성과측면의 실증결과를 통하여 한국주식시장에 있어서 시장수익률을 평균적으로 초과할 수 있는 거래전략은

• Journal of Broadcast Engineering
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• v.18 no.5
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• pp.691-701
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• 2013

In this paper, an early termination algorithm for merge process is proposed to reduce the computational complexity in High Efficiency Video Coding (HEVC) encoder. In the HEVC, the same candidate modes from merge candidate list (MCL) are shared to predict a merge or merge SKIP mode. This search process is performed by the number of the obtained candidates for the both of the merge and SKIP modes. This may cause some redundant search operations. To reduce this redundant search operation, we employ the neighboring blocks which have been encoded in prior, to check on the contextual information. In this study, the spatial, temporal and depth neighboring blocks have been considered to compute a correlation information. With this correlation information, an early termination algorithm for merge process is suggested. When all modes of neighboring blocks are SKIP modes, then the merge process performs only SKIP mode. Otherwise, usual merge process of HEVC is performed Through experimental results, the proposed method achieves a time-saving factor of about 21.25% on average with small loss of BD-rate, when comparing to the original HM 10.0 encoder.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11C
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• pp.1077-1087
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• 2003

In this paper, we proposed an architecture of a cryptosystem with various operating modes for the network security and implemented in hardware using the ASIC library. For configuring a cryptosystem, the standard block ciphers such as AES, SEED and 3DES were included. And the implemented cryptosystem can encrypt and decrypt the data in real time through the wired/wireless network with the minimum latency time (minimum 64 clocks, maximum 256 clocks). It can support CTR mode which is widely used recently as well as the conventional block cipher modes such as ECB, CBC and OFB, and operates in the multi-bit mode (64, 128, 192, and 256 bits). The implemented hardware has the expansion possibility for the other algorithms according to the network security protocol such as IPsec and the included ciphering blocks can be operated simultaneously. The self-ciphering mode and various ciphering mode can be supported by the hardware sharing and the programmable data-path. The global operation is programmed by the serial communication port and the operation is decided by the control signals decoded from the instruction by the host. The designed hardware using VHDL was synthesized with Hynix 0.25$\mu\textrm{m}$ CMOS technology and it used the about 100,000 gates. Also we could assure the stable operation in the timing simulation over 100㎒ using NC-verilog.

• The Transactions of the Korea Information Processing Society
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• v.6 no.9
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• pp.2294-2304
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• 1999

Our research purpose in this paper is to improve the performance of query processing in GIS(Geographic Information System) by enhancing the I/O performance exploiting parallel I/O and efficient disk access. By packing adjacent spatial data, which are very likely to be referenced concurrently, into one block or continuous disk blocks, the number of disk accesses and the disk access overhead for query processing can be decreased, and this eventually leads to the I/O time decrease. So, in this paper, we proposes EPR(Enhanced Parallel R-tree) indexing method which integrates the parallel I/O method of the previous Parallel R-tree method and a packing-based clustering method. The major characteristics of EPR method are as follows. First, EPR method arranges spatial data in the increasing order of proximity by using Hilbert space filling curve, and builds a packed R-tree by bottom-up manner. Second, with packing-based clustering in which arranged spatial data are clustered into continuous disk blocks, EPR method generates spatial data clusters. Third, EPR method distributes EPR index nodes and spatial data clusters on multiple disks through round-robin striping. Experimental results show that EPR method achieves up to 30% or more gains over PR method in query processing speed. In particular, the larger the size of disk blocks is and the smaller the size of spatial data objects is, the better the performance of query processing by EPR method is.