Design of a high performance 32*32-bit multiplier based on novel compound mode logic and sign select booth encoder (새로운 복합 모드 로직과 사인 선택 Booth 인코더를 이용한 고성능 32*32-bit 곱셈기의 설계)
-
- Journal of the Institute of Electronics Engineers of Korea SD
- /
- v.38 no.3
- /
- pp.51-51
- /
- 2001
-