• Journal of KIISE:Computer Systems and Theory
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• v.28 no.12
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• pp.685-697
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• 2001

Cache memories are small fast memories used to temporarily hold the contents of main memory that are likely to be referenced by processors so as to reduce instruction and data access time. In this paper, we represent analytical models of instruction fetch process for four types of instruction cache structures that can be used for superscalar processors. In the models, we define various kinds of architectural parameters and take cache miss and branch misprediction into consideration. To prove the correctness of the proposed models, we performed extensive simulations and compared the results with the analytical models. Simulation results showed that the proposed model can estimate the instruction fetch rate accurately within 10% error in most cases. Both analytical model and simulation show that the increase of cache misses reduces the instruction fetch rate more severely than that of branch misprediction does. However, the analytical model can explain the causes of performance degradation which cannot be uncovered by the simulation method only. The model is also able to provide exact relationship between cache miss and branch misprediction for instruction fetch analysis.

• The Korean Journal of Financial Management
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• v.16 no.1
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• pp.171-191
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• 1999

시간의 흐름에 걸친 주가시계열의 행동양식에 대한 연구에서는 선형성, 비선형성, 장기기억, 항상성분 등에 대한 명확한 결론을 내리고 있지 못한 실정이다. 주가 시계열과정을 설명하고 예측하기 위한 여러 모형들에 대한 실증연구에는 설명력과 예측력을 완벽하게 갖추고 있지 못하고 있다는 증거들이 제시되고 있다. 계절적 변동을 주가시계열에 적용하지 않는 관계로 이와 같은 결과가 발생할 가능성이 존재한다. 분기별 종합주가지수의 수익률에 계절적 단위근이 존재하고 있음이 실증분석을 통하여 밝혀졌다. 이 시계열에서는 계절적 단위근을 제거하기 위하여서는 제4계 시차 작용소가 적절한 필터임이 인정되었다. 월별 종합주가지수의 수익률에서도 계절적 단위근이 존재하고 있다. 따라서 제12계 시차 작용소를 사용하여 계절적 단위근을 제거하여야 할 것이다. 분기별 수익률에는 제4차 시차 작용소를, 월별수익률에서는 제12차 시차 작용소를 필터로 사용하여 이 시계열들을 차분화하고 이 차분화를 통하여 계절적 단위근을 제거한 후에 이 시계열들의 시계열적 성질과 특성을 탐구해야 할 것이다. 이 과정을 통할 때 시계열 과정에 대한 계량경제학적 모형에 대한 정확한 추론이 가능하게 된다.

• Fire Science and Engineering
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• v.22 no.3
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• pp.272-277
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• 2008

This study is performed for propose that exactly equivalent length of TBP in the applied at water-based fire protection system. For predict the measuring position of equivalent length, we determined the measuring position using the FVM about pressure drop of TBP. For the reckon of the exact about measured value we compared with the result of FVM and we knew the similar value each other. Using the results we proposed the friction loss measuring position that inlet of main dirction is 20 times of appellation diameter in main pipe, outlet of main dirction is 10 times of appellation diameter in main pipe and outlet of branched direction is 20 times of appellation diameter.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.7
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• pp.847-862
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• 1999

본 논문에서는 유한버퍼의(finite-buffered) 동기화된(synchronous) 큐잉모델(queueing model)을 이용하여 명령어들간의 병렬성, 분기명령의 빈도수, 분기예측(branch prediction)의 정확도, 캐쉬미스 등의 파라미터들을 고려하여 프로세서의 명령어 실행율을 예측하며 캐쉬의 성능과 파이프라인 성능간의 관계를 분석할 수 있는 새로운 해석적 모델을 제안하였다. 해석적 모델은 모델의 타당성을 검증하기 위해서 시뮬레이션을 수행하여 얻은 결과와 비교하였다. 해석적 모델과 시뮬레이션을 비교한 결과 대부분 10% 오차 내에서 일치하였다. 본 연구를 통하여 얻은 해석적 모델을 사용하면 시뮬레이션에서는 드러나지 않는 성능제약의 원인에 대한 명확한 규명이 가능하기 때문에 성능향상을 위한 설계자료를 얻을 수 있으며, 시스템 성능 밸런스를 위한 캐쉬와 비순차이슈 파이프라인 성능간의 관계에 대한 정확한 분석이 가능하다.Abstract This research presents a novel analytic model to predict the instruction execution rate of superscalar processors using the queuing model with finite-buffer size and synchronous operation mode. The proposed model is also able to analyze the performance relationship between cache and pipeline. The proposed model takes into account various kinds of architectural parameters such as instruction-level parallelism, branch probability, the accuracy of branch prediction, cache miss, and etc.. To prove the correctness of the model, we performed extensive simulations and compared the results with the analytic model. Simulation results showed that the proposed model can estimate the average execution rate accurately within 10% error compared to simulation results. The proposed model can explain the causes of performance bottleneck which cannot be uncovered by the simulation method only. The model is also able to show the effect of the cache miss on the performance of out-of-order issue superscalar processors, which can provide an valuable information in designing a balanced system.

• Proceedings of the Korea Information Processing Society Conference
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• 2019.10a
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• pp.456-458
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• 2019

정보보안을 달성하기 위해서 컴퓨터가 보급된 이래로 많은 노력이 이루어졌다. 그중 메모리 보호 기법에 대한 연구가 가장 많이 이루어졌지만, 컴퓨터의 성능 향상으로 이전의 메모리 보호 기법들의 문제들이 발견되고, 부채널 공격의 등장으로 새로운 방어책이 필요 되었다. 본 논문에서는 프로그램에 정적 바이너리 재작성(Static Binary Rewriting) 기법을 통해 페이지(Page)마다 4~8byte 의 난수를 삽입하여 메모리 공유 기반 부채널 공격을 방어할 수 있는 2 가지 방법을 제시한다. 최근 아키텍처는 분기 예측(Branch Prediction)을 통해 jmp 명령어에 대한 분기처리가 매우 빠르고 정확하게 처리되기 때문에 난수를 삽입할 때 사용하는 jmp+rand 방식은 오버헤드가 매우 낮다. 또한 특정 프로그램에만 난수 삽입이 가능하므로 특히 클라우드 환경에서 중복제거 기능과 함께 사용하면 높은 효율성을 보일 수 있다고 예상한다.

• Proceedings of the Korea Water Resources Association Conference
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• 2008.05a
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• pp.704-708
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• 2008

유역 통합 수자원 환경관리 시스템 내의 유출예측모듈인 RRFS를 통한 유출예측결과의 신뢰도 개선을 위해 ESP 기법을 금강유역에 적용하였다. 시나리오를 통해 생성된 유출예측 앙상블을 이용하여 50%의 확률값을 적용하여 본 결과 우리나라의 실정에 맞지 않아 예측의 결과를 적용하기 힘들고 수자원 관리의 정보로서 활용하기 힘들기 때문에 통계적인 분석을 통하여 정확도가 개선된 발생확률을 제시하기 위하여 본 연구를 수행하였다. 금강유역을 용담, 대청, 공주 지점으로 나눈 뒤, 유출량의 확률 예보를 위하여 '83년$\sim$'07년까지 25년간의 강우자료와 온도자료를 RRFS에 적용하여 '07년의 매월 25개의 유출 시나리오를 생성하였다. 생성된 유출 시나리오에서 Case별로 ESP확률을 산정하였다. 통계분석을 통해 얻어진 월별 ESP 확률분포를 이용하여 '02년부터 '07년까지 과거 실측 월별 유출량에 대한 ESP 확률범위를 결정하였고 년강수량의 2/3가 홍수기인 $6{\sim}9$월 사이에 집중되는 우리나라의 특성을 고려해 이수기(1월$\sim$6월 그리고 10월$\sim$12월)와 홍수기(7월$\sim$9월)로 분리한 후 각각에 대한 ESP 확률 값을 최종적으로 결정하였다. Case별로 '07년 금강유역에 적용한 결과, Case 2로 산정된 ESP확률 값이 다른 Case에 비해 더 적합한 것으로 나타났다. Case 1 큰 오차가 나는 ESP 확률을 제외한 평균 ESP확률의 적용, Case 2 월별 최소 오차가 나는 ESP확률의 적용, Case 3 Case2의 월별 ESP확률을 이수기 홍수기로 평균한 ESP확률 적용, Case 4 분기별 최소 오차가 나는 ESP확률의 적용, Case 5 Case4의 분기별 ESP확률을 이수기 홍수기로 평균한 ESP확률의 적용.

• Journal of Intelligence and Information Systems
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• v.29 no.3
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• pp.361-381
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• 2023

Research on corporate bankruptcy prediction has been focused on financial information. Since the company's financial information is updated quarterly, there is a problem that timeliness is insufficient in predicting the possibility of a company's business closure in real time. Evaluated companies that want to improve this need a method of judging the soundness of a company that uses information other than financial information to judge the soundness of a target company. To this end, as information technology has made it easier to collect non-financial information about companies, research has been conducted to apply additional variables and various methodologies other than financial information to predict corporate bankruptcy. It has become an important research task to determine whether it has an effect. In this study, we examined the impact of electronic payment-related information, which constitutes non-financial information, when predicting the closure of business operators using electronic payment service and examined the difference in closure prediction accuracy according to the combination of financial and non-financial information. Specifically, three research models consisting of a financial information model, a non-financial information model, and a combined model were designed, and the closure prediction accuracy was confirmed with six algorithms including the Multi Layer Perceptron (MLP) algorithm. The model combining financial and non-financial information showed the highest prediction accuracy, followed by the non-financial information model and the financial information model in order. As for the prediction accuracy of business closure by algorithm, XGBoost showed the highest prediction accuracy among the six algorithms. As a result of examining the relative importance of a total of 87 variables used to predict business closure, it was confirmed that more than 70% of the top 20 variables that had a significant impact on the prediction of business closure were non-financial information. Through this, it was confirmed that electronic payment-related information of non-financial information is an important variable in predicting business closure, and the possibility of using non-financial information as an alternative to financial information was also examined. Based on this study, the importance of collecting and utilizing non-financial information as information that can predict business closure is recognized, and a plan to utilize it for corporate decision-making is also proposed.

• Korean Journal of Construction Engineering and Management
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• v.13 no.6
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• pp.54-62
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• 2012

Currently, construction engineering industry of high value and rapid growing has been viewed as a future oriented industry. Thus, compared to other industries, its analysis system for business trend seems insufficient. This research has developed a business survey index model targeted for construction engineering industries, and business trends for 4/4 quarter of 2011 as well as 1/4 quarter of 2012 were surveyed as important traits were analyzed. Business Survey Index of Construction Engineering has been constructed in form of an index in order to accurately judge different economic states of the industry such as funding areas, human resources, payability, ordering scale, status of domestic and foreign markets, Difficulties in Management, and improvements in policies. In the future, CEBSI will not only be applied on the construction engineering industry, but it will also be used as the economic state of all construction industries as well as the prospect data. Thus, it will be utilized as basic resources that can establish systematic and accurate policies.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.35 no.10
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• pp.940-947
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• 2007

For the performance upgrade of a supersonic jet fighter, the processor and FLCC(Flight Control Computer) Architecture were upgraded from a baseline FLCC. Prior to the hardware implementation phase, the exact CPU throughput estimation is necessary. For this purpose, an experimental method for new FLCC throughput estimation was introduced in this study.　While baseline FLCC operating, the CPU address bus was collected with logic analyzer, and then decoded to get the exact access times to each memory-memory and the number of program Instruction branches. Based on these data, a throughput test in CPU demo-board of the new FLCC configuration was performed. From test results, the CPU-Memory architecture was design-changed before FLCC hardware implementation phase. To check the flight stability degradation due to power-interrupt problem due to CPU-Memory architecture change, the piloted HILS (Hardware-In-the Loop Simulator) test was conducted.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.1083-1086
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• 2005

Modern superscalar processors exploit Instruction Level Parallelism to achieve high performance by speculative techniques such as branch prediction. The indirect branch target prediction is very difficult compared to the prediction of direct branch target and branch direction, since it has dynamically polymorphic target. We present a accurate and hardware-efficient indirect branch target predictor. It can reduce the tags which has to be stored in the Indirect Branch Target Cache without a sacrifice of the prediction accuracy. We implement the proposed scheme on SimpleScalar and show the efficiency running SPEC95 benchmarks.