• The KIPS Transactions:PartB
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• v.16B no.2
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• pp.123-130
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• 2009

Motion estimation (ME) plays an important role in digital video compression. But it limits the performance of image quality and encoding speed and is computational demanding part of the encoder. To reduce computational time and maintain the image quality, integer pel and fractional pel ME methods are proposed in this paper. The proposed method for integer pel ME uses a hierarchical search strategy. This strategy method consists of symmetrical cross-X pattern, multi square grid pattern, diamond patterns. These search patterns places search points symmetrically and evenly that can cover the overall search area not to fall into the local minimum and to reduce the computational time. The proposed method for fractional pel uses full search pattern, center biased fractional pel search pattern and the proposed search pattern. According to block sizes, the proposed method for fractional pel decides the search pattern adaptively. Experiment results show that the speedup improvement of the proposed method over Unsymmetrical cross Multi Hexagon grid Search (UMHexagonS) and Full Search (FS) can be up to around $1.2{\sim}5.2$ times faster. Compared to image quality of FS, the proposed method shows an average PSNR drop of 0.01 dB while showing an average PSNR gain of 0.02 dB in comparison to that of UMHexagonS.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.107-108
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• 2014

부화소 기반 영상 축소기법은 각각의 부화소를 조절함으로써 픽셀 기반 영상 축소기법보다 해상도를 향상시킬 수 있는 방법이다. 그러나 부화소에 의한 해상도의 증가는 종종 색상정보의 왜곡을 발생시킨다. 부화소 랜더링의 주요과제는 선명도를 유지함과 동시에 색조왜곡현상을 억제하는 것이다. 선행연구들은 부화소랜더링을 위해 1 차원 혹은 2 차원 필터를 최적화 하였지만, 지역적인 특성을 고려하지 않았기 때문에 출력영상의 화질이 저하되는 현상이 발생한다. 본 논문은 위와 같은 문제를 해결하기 위해 내용적응형 2D FIR 필터를 제작방법을 제안한다. 제안필터는 충분한 수의 저해상도 패치와 고해상도 패치 쌍을 이용하여 임의의 고해상도 패치로부터 고화질의 저해상도 패치를 만들기 위한 최적의 내용적응형 2D FIR 필터를 학습한다. 학습된 필터에 의한 실험결과 제안하는 필터가 종례기법들 보다 색조왜곡현상이 현저히 줄어들고, 출력영상의 선명도를 유지함을 보여준다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.3
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• pp.74-79
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• 2008

In an H.264/AVC video encoder, the motion estimation at fractional pixel accuracy improves a coding efficiency and image quality. However, it requires additional computation overheads for fractional search and interpolation, and thus, reducing the computation complexity of fractional search becomes more important. This paper proposes fast fractional search algorithms by combining the SASR(Simplified Adaptive Search Range) and the MSDSP(Mixed Small Diamond Search Pattern) with the predicted fractional motion vector. Compared with the full search and the prediction-based directional fractional pixel search, the proposed algorithms can reduce up to 93.2% and 81% of fractional search points, respectively with the maximum PSNR lost less than 0.04dB. Therefore, the proposed fast search algorithms are quite suitable for mobile applications requiring low power and complexity.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.1
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• pp.64-70
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• 2011

In an H.264/AVC video encoder, the motion estimation at fractional pixel accuracy improves a coding efficiency and image quality. However, it requires additional computation overheads for fractional search and interpolation, and thus, reducing the computation complexity of fractional search becomes more important. This paper proposes a Pixel Re-composition Fractional Motion Estimation (PRFME) algorithm for an H.264/AVC video encoder. Fractional Motion Estimation performs interpolation for the overlapped pixels which increases the computational complexity. PRFME can reduce the computational complexity by eliminating the overlapped pixel interpolation. Compared with the fast full search, the proposed algorithm can reduce 18.1% of computational complexity, meanwhile, the maximum PSNR degradation is less than 0.067dB. Therefore, the proposed PRFME algorithm is quite suitable for mobile applications requiring low power and complexity.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2017.06a
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• pp.149-150
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• 2017

본 논문에서는 RGB-stripe 부화소 구조를 갖는 디스플레이에서 인지 화질을 향상시키면서, 색 왜곡을 저감할 수 있는 부화소 렌더링을 수행한다. 우선 인지 화질을 향상 시키는 주 필터와, 색 왜곡을 억제하는 비음수 필터를 디자인한다. 색 왜곡 가능성의 계산에 따라, 두 필터를 조합하고 영상을 렌더링 한다. 실험 결과, 본 논문의 부화소 렌더링 방법이 비교 방법에 비해 좋은 인지 화질을 얻으면서도 색 왜곡을 억제함을 보여준다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2017.11a
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• pp.107-109
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• 2017

HEVC 표준은 정수 화소로 표현된 신호에 DCT-II 를 기반으로 하는 보간 필터를 사용하여 부화소 신호를 생성한다. 움직임 보상 및 예측의 성능 향상을 위해서 부화소 신호를 생성하는 방법을 이용한다. HEVC 표준은 부화소를 각각 1/4-화소 단위로 생성을 하며, 부화소를 생성하기 위해서 길이가 다른 각각의 DCT 보간 필터를 사용하고 있다. 1/2-화소를 생성하는 경우에는 필터의 길이가 8 인 DCT 기반 보간 필터를 사용하며, 1/4-화소와 3/4-화소의 경우에는 필터의 길이가 7 인 DCT 기반 보간 필터를 사용한다. 본 논문에서는 DST-VII을 기반으로 하는 보간 필터를 제안하여, CTU-Level 단위로 RDO 과정을 통해 최적화된 보간 필터를 선택하여 사용한다. 본 논문에서 제안하는 방법은 HEVC 표준보다 BD-rate 가 Low Delay B 와 Random Access configurations 에서 각각 0.6%와 0.6%의 성능 향상을 가져오며 Low Delay P configuration 에서 0.5%의 성능감소를 보인다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.1
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• pp.103-119
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• 2010

In this paper, we propose a subpixel shift estimation method using phase correlation with a local region for the registration of noisy images. Phase correlation is commonly used to estimate the subpixel shift between images, which is derived from analyzing shifted and downsampled images. However, when the images are affected by additive white Gaussian noise and aliasing artifacts, the estimation error is increased. Thus, instead of using the whole image, the proposed method uses a specific local region that is less affect by noises. In addition, to improve the estimation accuracy, iterative phase correlation is applied between selected local regions rather than using a fitting function. the restricted range is determined by analyzing the maximum peak and the two adjacent values of the inverse Fourier transform of the normalized cross power spectrum. In the experiments, the proposed method shows higher accuracy in registering noisy images than the other methods. Thus, the edge-sharpness and clearness in the super-resolved image is also improved.

• Korean Journal of Animal Reproduction
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• v.22 no.2
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• pp.163-169
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• 1998

본 실험은 체외 생산된 소 배반포기배에 대한 laser drilling 처리가 배의 부화율에 미치는 영향을 조사하고자 실시하였다. 그 결과는 다음과 같다. 소 수정란의 체외 발달율을 조사하였던 바, 82.3%의 난할율( 2-세포기)과 체외수정 후 배양 7일째에 32.6%의 배반포 발달율을 나타내었다. 이렇게 생산된 배반포기배에 laser drilling 효과를 조사하였던 바, 처리 후 24시간째의 부화진행율(90.0%)은 대조군(44.4%)보다 유의하게 높게 나타났다(p<0.0001). 또한, 처리 후 48시간째의 부화율(68.0%)도 대조군(33.3%)보다 유의하게 높게 나타났다. 이러한 결과는 laser drilling이 체외 생산된 소 배반포기배의 부화진행율과 부화율을 유의하게 증가시킬 수 있다는 것을 알 수 있었다(p<0.001).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.2
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• pp.372-379
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• 2015

The latest video compression standard (such as H.264/AVC and HEVC) utilizes quarter-pel accuracy motion estimation in order to retain detailed motion information. Many sub-pixel motion estimation algorithms used in the spatial domain usually encounters increment of computational complexity due to embedded interpolation algorithm. In this paper, an approach to measure sub-pixel accuracy motion estimation in frequency domain using shifting matrix is proposed. Complexity can be reduced utilizing shifting matrix algorithm in frequency domain and simulation results demonstrate not only higher PSNR but lower bit rates than spatial domain algorithms.

• The KIPS Transactions:PartA
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• v.18A no.6
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• pp.249-254
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• 2011

This paper describes an efficient design of the interpolation circuit to generate the luma and chroma sub-pixels for H.264 motion estimation. The circuit based on the proposed architecture does not require any input data buffering and processes the horizontal, vertical and diagonal sub-pixel interpolations in parallel. The performance of the circuit is further improved by simultaneously processing the 1/2-pixel and 1/4-pixel interpolations for luma components and the 1/8-pixel interpolations for chroma components. In order to reduce the circuit size, we store the intermediate data required to process all the interpolations in parallel in the internal SRAM's instead of registers. We described the proposed circuit at register transfer level and verified its operation on FPGA board. We also synthesized the gate-level circuit using 130nm CMOS standard cell library. It consists of 20,674 gates and has the maximum operating frequency of 244MHz. The total number of SPSRAM bits used in our circuit is 3,232. The size of our circuit (including logic gates and SRAM's) is smaller than others and the performance is still comparable to them.