• KIISE Transactions on Computing Practices
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• v.21 no.7
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• pp.476-481
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• 2015

We have parallelized the cumulative sum (CUSUM) test of NIST's statistical random number test suite in a CUDA environment. Storing random walks in an array instead of in scalar variables eliminates data dependence. The change in data structure makes it possible to apply parallel scans, scatters, and reductions at each stage of the test. In addition, serial data exchanges between CPU and GPU are removed by migrating CPU's tasks to GPU. Finally we have optimized global memory accesses. The overall speedup is 23 times over the sequential version. Our results contribute to improving security of random numbers for cryptographic keys as well as reducing the time for evaluation of randomness.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.205-206
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• 2016

본 논문에서는 전압 밸런싱을 위한 부스트-포워드 컨버터를 이용한 피드백 방식 차동전력조절(DPP, Differential Power Processing) 시스템을 제안한다. 이 시스템은 서로 직렬 연결된 태양광패널을 입력으로 연결된 상태에서 DPP 컨버터가 각 태양광패널에 병렬로 연결된다. 또한 DPP 컨버터의 출력도 직렬로 연결되고 전체는 부스트 컨버터에 의해 통합되어 최종적으로 인버터를 통해 계통 및 기타 시스템에 연결된다. 이러한 구조의 DPP 시스템은 태양광패널 중의 한 부분에 그늘짐 현상이 발생할 경우 DPP 컨버터의 출력에 영향을 미치게 되어 전압불균형이 발생한다. 이는 전체 시스템의 효율과 인버터와 같은 계통과 연결 시 정상작동 여부에 큰 영향을 미칠 수 있기 때문에 DPP 컨버터 출력부의 전압 밸런싱을 수행하는 회로가 필요하다. 제안하는 회로는 이러한 DPP 시스템에서 적용할 수 있는 부스트-포워드 컨버터를 이용한 전압 밸런싱 회로이다. 이를 검증하기 위하여 컴퓨터 시뮬레이션을 이용하였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.2 s.105
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• pp.124-128
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• 2006

In this paper, Compact Microstrip Resonant Cell(CMRC)s have been employed to suppress IMD(Intermodulation Distortion) of the 3-Way Doherty amplifier. This method can not only improve the linearity and the efficiency but also be simpler, smaller and more inexpensive than existing linearity methods; (for example harmonic feedback, back off, feed-forward, predistortion and so on) Also, using only one divider reduces the size of the proposed 3-Way Doherty amplifier. As a result, the IMD3 and the PAE have been improved by 4.5 dB and by $9.2\%$, respectively, using the proposed Doherty amplifier with CMRC.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.940-948
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• 2008

This paper presents a low-power, low-complexity design and implementation results of a high speed multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN (WLAN) baseband processor. The proposed processor is composed of the physical layer convergence procedure (PLCP) processor and physical medium dependent (PMD) processor, which have been optimized to have low-power and reduced-complexity architecture. It was designed in a hardware description language (HDL) and synthesized to gate-level circuits using 0.18um CMOS standard cell library. As a result, the proposed TX-PLCP processor reduced the power consumption by as much as 81% over the bit-level operation architecture. Also, the proposed MIMO symbol detector reduced the hardware complexity by 18% over the conventional SQRD-based architecture with division circuits and square root operations.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.1
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• pp.131-141
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• 2007

This paper proposes analysis on new equipment for power quality in electric railway. The proposed equipment consists of series inverter and parallel inverter. Each inverter is connected by capacitor as dc link. This structure can be compensated for active and reactive power in catenary through transformer. We verified the proposed equipment using the PSCAD/EMTDC and the calculation results from the proposed approach are widely described in the paper.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.37 no.5
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• pp.115-123
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• 2000

In this paper, a block FIR(Finite Impulse Response) filtering architecture is proposed for IF digital down converter. Digital down converter consists of digital mixers. decimation filters and down samplers. In this proposed structure, it is shown that a efficient parallel decimation filter architecture can be produced by cancellation of inherent up sampling of the block filter and following down sampler Furthermore. it is shown that computational complexity of the proposed architecture is reduced by exploiting the block FIR structure and zero values of the digital mixers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5A
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• pp.743-750
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• 2000

In this paper, low-power block filtering architecture for digital If down sampler and up sampler is proposed. Software radio technology requires low power and cost effective digital If down and up sampler. Digital If down sampler and up sampler are accompanied with decimation filter and interpolation filter, respectively. In the proposed down sampler architecture, it is shown that the parallel and low-speed processing architecture can be produced by cancellation of inherent up sampler of block filter and down sampler. Proposed up sampler also utilizes cancellation of up sampler and inherent down sampler of block filtering structure. The proposed architecture is compared with the conventional polyphase architecture.

• Proceedings of the KSME Conference
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• 2004.04a
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• pp.810-815
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• 2004

In this paper, we propose new parallel mechanism of a 3 dimensional biped robot whose each leg is composed of two 3-dof parallel platforms linked serially. This proposed parallel mechanism is able to move freely in the man-made environment and is applied to various fields, such as medical, welfare, and so on. And a total weight of each leg is expected to be lighter than serial linked leg. One side leg consists of a 3-dof orientation platform and 3-dof asymmetric parallel platform. The former consists of three active linear actuators and seven passive joints, and the latter of two active linear actuators, one active rotational actuator and eight passive joints. Thus, there are two kinds of parallel platforms each chain's elements and active joint's positions are different for the biped robot to move freely like a serial link without the kinematics constraints. The effectiveness and the performance of the proposed parallel mechanism and locomotion trajectory are shown in computer simulations with a 12-DOF parallel biped robot.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.4
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• pp.350-357
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• 2016

In this paper, a small mu-zero zeroth order resonance(ZOR) antenna based on meta structure is proposed using parasitic patch at 5.8 GHz. The mu-zero ZOR antenna is designed by utilizing the resonance of series inductance and capacitance of mu-negative transmission line and its size can be further reduced by a simple parasitic patch. The parasitic patch can increase series capacitance of mu-negative transmission line related to a resonant frequency. We have simulated and optimized dimension of the parasitic patch using Ansys commercial simulator(HFSS). As a result, the antenna has the following characteristics: kr of 0.59, efficiency of 92 %, and gain of 6.57 dBi. Also, its size is reduced by 24 % compared to a conventional mu-zero ZOR antenna. The measured results are in good agreement with the simulated results.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1297-1298
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• 2007

염료 감응형 태양전지(DSSC)의 개발 이후 많은 연구와 실험이 상용화를 위한 대면적화에 중점을 두고 진행되고 있다. 대면적화에 대한 대부분의 연구에서 그리드 전극을 넣고 내부적으로 직, 병렬 구조를 조합해 확장 시키는 방법을 채택하고 있지만, 그리드 전극을 넣음으로써 발생하는 손실, 즉 실링 공정의 어려움으로 발생하는 전자의 손실과 제작 공정상에 있어서의 복잡한 절차 및 그에 따라 소요되는 시간 등을 감안할 때 이는 그리 효과적이지 못하다고 할 수 있다. 면적이 작은 여러 셀을 외부에서 연결시켜 대면적화 시켰을 때 그 효과에 대해서 알아보고, 동일한 면적의 대면적화 된 단일 셀과 비교, 그 결과를 분석해 보았다. 그 결과, 우리는 동일한 면적을 가지고 있는 대면적의 단일 셀보다 여러 셀의 병렬 조합으로 이루어진 것이 더 좋은 결과를 나타냄을 알 수 있었다. 이를 바탕으로 유효면적 $8cm^2$을 가지는 셀을 외부적으로 연결시켜 대면적화 시켰을 때 그 효과에 대해서 알아보고 실험하였다. 하나의 모듈을 만들기 위해 직 병렬의 다양한 조합을 시도하여 직렬 연결이 많이 된 모듈일수록 이를 다시 병렬로 연결했을 때 전류의 손실을 많이 줄일 수 있다는 결론을 얻었다.