• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.5
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• pp.937-941
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• 2016

This paper proposed an efficient multiple TCP mechanism using Android smartphones for remote control video Wi-Fi stream transmission via network communications in real time. The wireless video stream transmission mechanism can be applied in various area such as real time server stream transmissions, movable drones, disaster robotics and real time security monitoring systems. Moreover, we urgently need to transmit data in timely fashion such as medical emergency, security surveillance and disaster prevention. Our parallel TCP transmission system can play an important role in several area such as real time server stream transmissions, movable drones, disaster robotics and real time security monitoring systems as mentioned in the previous sentence. Therefore, we designed and implemented a parallel TCP transmission (parallel stream) for an efficient real time video streaming services. In conclusion, we evaluated proposed mechanism using parallel TCP transmission under various environments with performance analysis.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.11B
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• pp.1254-1260
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• 2009

This paper proposes history-aware random early detection (HRED), a modified version of RED, to lessen bandwidth monopoly by a few of stations employing multiple parallel TCP flows. Stations running peer-to-peer file sharing applications such as BitTorrent use multiple TCP flows. If those stations share a link with other stations with only a small number of TCP flows, the stations occupy most of link bandwidth leading to undesirable bandwidth monopoly. HRED like RED determines whether to drop incoming packets according to probability which changes based on queue length. However it adjusts the drop probability based on bandwidth occupying ratio of stations, thus able to impose harder drop penalty on monopoly stations. The results of simulations assuming various scenarios show that HRED is at least 60% more effective than RED in supporting the bandwidth fairness among stations and at least 4% in utilization.

• Proceedings of the Korea Information Processing Society Conference
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• 2000.10b
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• pp.1259-1262
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• 2000

반도체 제조장비로 구성된 통신 시스템은 일반적으로 직렬통신, 병렬통신, TCP/IP 통신 또는 별도의 개발 시스템을 사용한다. 기존의 단일장비 모니터링 시스템은 동일한 통신시스템을 사용하는 장비들의 그룹만을 모니터링 하는 시스템이다. 그러나 다양한 반도체 제조장비의 모니터링을 위해서는 통신 장비들의 추가 변경이 가능한 구조가 요구된다. 본 논문은 기존의 단일 장비 모니터링 시스템의 한계를 보완하여 직렬통신장비, 병렬통신장비, iQ 망 통신, TCP/IP 통신을 하는 반도체 제조장비의 통합 모니터링을 위한 통신 시스템 구조를 제시한다.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.6
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• pp.1045-1054
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• 2020

In this paper, we designed a TCP/IP based ring buffer system that can stably transfer bulk data streams in the unstable network environments. In the scheme we proposed, The observation data stream generated and output by each radio observatory's backend system as a UDP frame is stored as a UDP packet in a large capacity ring buffer via a socket buffer in the client system. Thereafter, for stable transmission to the remote destination, the packets are processed in TCP and transmitted to the socket buffer of server system in the correlation center, which packets are stored in a large capacity ring buffer if there is no problem with the packets. In case of errors such as loss, duplication, and out of order delivery, the packets are retransmitted through TCP flow control, and we guaranteed that the reliability of data arriving at the correlation center. When congestion avoidance occurs due to network performance instability, we also suggest that performance degradation can be minimized by applying parallel streams.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.600-602
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• 2000

본 논문에서는 여러 개의 디스크를 클러스트화한 메시지 전송 기반의 병렬 멀티미디어 파일 시스템(PMFS: Parallel Multimedia File System)을 제안하고 설계, 구현하였다. 본 논문에서 구현한 PMFS는 이식성, 유연성 그리고 확장성을 고려한 멀티미디어 데이터를 지원하는 병렬 파일 시스템으로 2계층 분산 클러스트 구조에 적합하다. 그리고 제어 메시지와 TCP를 기반으로 서버들간에 통신을 하고 다양한 방법의 데이터 배치 기법을 제공한다. PMFS의 성능 평가 결과 데이터들이 임의 시작 블록과 DIS배치 기법으로 저장된 경우 가장 좋은 성능을 보였다.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.10
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• pp.539-549
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• 2002

PC cluster-based Information Retrieval (IR) systems improve their performances by parallel processing of query terms using cluster nodes. However TCP/IP based communication used to exchange data between cluster nodes prevents the performance from being improved further. The user-level communication mechanisms solve the problem by eliminating the time-consuming kernel access in exchanging data between cluster nodes. The Virtual Interface Architecture (VIA) is one of the representative user-level communication mechanisms which provide low latency and high bandwidth. In this paper, we propose a VIA-based parallel IR system on a PC cluster. The IR system is implemented using the following three communication methods: Sealable Coherent Interface (SCI) based VIA, MPI on SCI based VIA, MPI on Fast Ethernet based VIA. Through experiments, the performances of the three methods are analyzed in various aspects.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.04a
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• pp.808-811
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• 2010

최근 네트워크를 구성하는 기반 시설의 성능이 향상됨에 따라 대량의 트래픽에 대한 네트워크 침입탐지 시스템의 성능을 향상시키기 위한 연구가 진행되고 있다. 대규모 네트워크에서는 단일 시스템으로 네트워크 내의 모든 트래픽을 분석하는 것이 불가능하므로 병렬 구조 NIDS를 도입하여야 하는데, 이를 위해서는 병렬 구조를 이루는 각 NIDS 노드로의 부하 분산이 필요하다. 플로우 기반 부하 분산 기법은 이러한 부하 분산 기법 중 하나로, TCP 세그먼트의 재조합으로 인해 발생하는 통신 오버헤드를 줄일 수 있어 효율적이다. 본 논문에서는 네트워크 트래픽의 특성과 각 노드의 성능을 고려하여 플로우 기반 부하 분산이 효율적으로 이루어질 수 있는 방안을 제안한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.10
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• pp.2164-2170
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• 2011

Rapid surge in date quantity lead to increase in storage demand from corporate. The existing SAN with fiber channel is being changed to IP-based SAN environment due to installment and maintenance cost. But the IP-based network still have some similar security problems as existing TCP/IP network. Also, for the security reasons of storage traffic, data are encrypted, but with the existing system, data larger than 10G can't be handled. To address security and speed issue, this paper proposes to a structure applied to IP SAN environment with Parallel Structure Word-based FSR (PS-WFSR) as hardware.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1166-1174
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• 2004

In this paper, a design of RISC-based transmission wrapper processor for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability, and memory module. To handle the various modes of TCP/IP protocol, hardware-software codesign approach based on RISC processor is used rather than the conventional state machine design. To eliminate large delay time due to sequential executions of data transfer and checksum operation, DMA module which can execute the checksum operation along with data transfer operation is adopted. The designed processor exclusive of variable-size input/output buffer consists of about 23,700 gates and its maximum operating frequency is about 167MHz under 0.35${\mu}m$ CMOS technology.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.7
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• pp.1289-1295
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• 2007

In this paper, we implemented high-performance concurrent control system which manages whole RF systems with digital type and communicates with remote station on both wire and wireless networking. It consists of FPGA (Field Programmable Gate Array) part which controls forward/reverse LPA (Linear Power Amplifier), forward/reverse LNA (Low Noise Amplifier), channel cut wire/wireless TCP/IP, etc, master microprocessor (AVR), which manages the whole control system, Slave microprocessor which communicates SA (Spectrum Analyzer) and observes frequency spectrum of each channel with the resolution of 5KHz, 10 channel card microprocessor which independently observes each channel card and sets frequency synthesizer in channel cut and other peripherals and logics. The whole system is divided to two parts of H/W (hardware) and S/W (software) considering operational efficiency and concurrency, and implementation and cost. H/W consists of FPGA and microprocessor. We expected the optimized operation through H/W and SW co-design and hybrid H/W architecture.