• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.6
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• pp.1441-1446
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• 2014

For the escape from a maze, the cooperative method by robot swarm was proposed in this paper. The robots can freely move by collecting essential data and making a decision in the use of sensors; however, a central control system is required to organize all robots for the escape from the maze. The robots explore new mazes and then send the information to the system for analyzing and mapping the escaping route. Three issues were considered as follows for the effective escape by multiple robots from the mazes in this paper. In the first, the mazes began to divide and secondly, dead-ends should be blocked. Finally, after the first arrivals at the destination, a shortcut should be provided for rapid escaping from the maze. The parallel-escape algorithms were applied to the different size of mazes, so that robot swarm can effectively get away the mazes.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.335-338
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• 2017

Currently Artificial Inteligence and Deep Learning are social issues, and These technologies are applied to various fields. A good method among the various algorithms in Artificial Inteligence is Convolutional Neural Network. Convolutional Neural Network is a form that adds convolution layers that extracts features by convolution operation on a general neural network method. If you use Convolutional Neural Network as small amount of data, or if the structure of layers is not complicated, you don't have to pay attention to speed. But the learning time is long as the size of the learning data is large and the structure of layers is complicated. So, GPU-based parallel processing is a lot. In this paper, we developed Convolutional Neural Network using CUDA and Learning speed is faster and more efficient than the method using the CPU.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.217-219
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• 2018

The method on reconfiguring job priority in service queue has been developed to provide seamless service and to enhance operability of Data Service Platform(DSP) in Korean e-Navigation project that performed by Ministry of Oceans and Fisheries(MOF) since 2016. It plays a critical role for providing seamless services of DSP to expect which services ships request to DSP and how much time it costs to make services for responding them to ships in advance. Therefore, as developing a method on reconfiguring jobs in service queue of DSP with a noble algorithm to analyse priority index in parallel, DSP can provide seamless services to ships regardless of data volume and the number of requests that stacked in service queue.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8B
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• pp.1493-1498
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• 2000

In this paper, we introduce a modified interference cancellation scheme to overcome MAI in DS-CDMA. Among ICs(Interference Cancellers), PIC(Parallel IC) requires the more complexity, and SIC(Successive IC) faces the problems of the long delay time. Most of all, the adaptive detector achieves the good BER performance using the adaptive filter conducted iteration algorithm. so it requires many iterations. To resolve the problems of them, we propose an improved adaptive detector that the received signal removed MAI through the sorting scheme and the cancellation method are fed into the adaptive filter. Because the improved input signal is fed into the adaptive filter, it has the same BER performance only using smaller iterations than the conventional adaptive detector, and the proposed detector having adaptive filter requires less complexity than the other detectors.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.9
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• pp.1867-1879
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• 1997

DREAM-S is a distributed main-memory database system for the real-time processing of shared operational datra in ATM switching systems. DREAM-S has a client-server architecture in which only the server has the diskstorage, and provides the T-Tree index structure for efficient accesses to the data. We propose a recovery technique for the T-Tree index structre in DREAM-S. Although main-memory database system offer efficient access performance, the database int he main-memory may be broken when system failure such as database transaction failure or power failure occurs. Therfore, a recovery technique that recovers the database (including index structures) is essential for fault tolerant ATM switching systems. Proposed recovery technique relieves the bottleneck of the server processors disk operations by maintaining the T-Tree index structure only in the main-memory. In addition, fast recovery is guaranteed even in large number of client systems since the T-Tree index structure(s) in each system can be recovered cncurrently.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.6A
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• pp.640-647
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• 2006

This paper describes a design of AES-based CCMP(Counter mode with CBC-MAC Protocol) core for IEEE 802.11i wireless LAN security. To maximize the performance of CCMP core, two AES cores are used, one is the counter mode for data confidentiality and the other is the CBC node for authentication and data integrity. The S-box that requires the largest hardware in ARS core is implemented using composite field arithmetic, and the gate count is reduced by about 27% compared with conventional LUT(Lookup Table)-based design. The CCMP core was verified using Excalibur SoC kit, and a MPW chip is fabricated using a 0.35-um CMOS standard cell technology. The test results show that all the function of the fabricated chip works correctly. The CCMP processor has 17,000 gates, and the estimated throughput is about 353-Mbps at 116-MHz@3.3V, satisfying 54-Mbps data rate of the IEEE 802.11a and 802.11g specifications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.3B
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• pp.179-187
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• 2002

This paper proposes and analyzes the iterative groupwise equal-delay interference cancellation(IGEIC) algorithm for coherent detection of an asynchronous wideband DS-CDMA system in a single cell over multipath fading channels. The IGEIC algorithm divide users in a system into several groups, and subtract out interference signal from the received signal as many as the number of users within a user group, iteratively. The IGEIC algorithm is also classified into the iterative groupwise equal-delay serial interference cancellation(IGESIC) algorithm and the iterative groupwise equal-delay parallel interference cancellation(IGEPIC) algorithm. In the case of perfect correlation for spreading codes, it shows that the performance of IGESIC and IGEPIC algorithm is the same after interference cancellation of as many as the number of users within a user group, but the performance of IGEPIC algorithm is superior to the IGESIC algorithm just before fecal cancellation within a user group. The results show that (he performance of the two proposed algorithms are also superior to the SIC algorithm by 3dB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.4C
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• pp.277-282
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• 2012

In this paper, we present a real-time eye contact system for realistic telepresence using a Kinect depth camera. In order to generate the eye contact image, we capture a pair of color and depth video. Then, the foreground single user is separated from the background. Since the raw depth data includes several types of noises, we perform a joint bilateral filtering method. We apply the discontinuity-adaptive depth filter to the filtered depth map to reduce the disocclusion area. From the color image and the preprocessed depth map, we construct a user mesh model at the virtual viewpoint. The entire system is implemented through GPU-based parallel programming for real-time processing. Experimental results have shown that the proposed eye contact system is efficient in realizing eye contact, providing the realistic telepresence.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.1
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• pp.58-70
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• 1990

This paper describes a VLSI implementation of real-time two dimensional DCT processor for the subprimary rate video codec system. The proposed architecture exploits the parallelism and concurrency of the distributes architecture for vector inner product operation of DCT and meets the CCITT performance requirements of video codec for full CSIF 30 frames/sec. It is also shown that this architecture satisfies all the CCITT IDCT accuracy specification by simulating the suggested architecture in bit level. The efficient VLSI disign methodology to design suggested architecture is considered and the module generator oriented design environments are constructed based on SUN 3/150C workstation. Using the constructed design environments. the suggensted architecture have been designed by double metal 2micron CMOS technology. The chip area fo designed 8x8 2-D DA-DCT (Distributed Arithmetic DCT) processor is about 3.9mmx4.8mm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.2
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• pp.159-167
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• 1992

This paper describes a feature extraction process by using a multi-layer neural network and is applied to the Korean stroke pattern for on line hand written character recognition, In the first layer the features are detected during the writing process and in the second layer the stroke specific features are extracted. A modified Masking field algorithm for direction co9nstancy has been used in this neural network and the resulting action potential of stroke specific features represents statistical distribution of the features in the on-line input stroke pattern and these results can be used in the recognition of on-line hand written Korean characters successfully.