• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2018.06a
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• pp.164-165
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• 2018

2017년 3월에 NVIDIA에서 출시한 Jetson TX2는 GPU를 탑재한 고성능의 임베디드 보드이다. 이 제품은 GPU를 이용한 병렬 처리를 통해 임베디드 시스템 상에서 연산량이 많은 알고리즘을 동작시킬 수 있다. 스테레오 매칭 기법은 스테레오 카메라를 이용하여 깊이 정보를 획득할 수 있으며, 획득한 깊이 정보는 다양한 어플리케이션의 메타 데이터로써 활용될 수 있다. 하지만 알고리즘의 연산량이 매우 많아 GPU를 탑재한 데스크톱에서만 동작하는 것이 일반적이었다. 이에 본 논문은 임베디드 보드인 Jetson TX2에서 기존에 개발되었던 스테레오 매칭 알고리즘들을 동작시키고 성능 분석을 통해 실시간 동작 여부에 대한 연구를 진행하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.11a
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• pp.75-78
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• 2013

본 연구에서는 멀티코어 기반의 안드로이드 부팅 최적화 방법을 제안하고 있다. 안드로이드 부팅 구간 중 Zygote란 프로세스 초기화 과정 시 가장 많은 연산을 하고 있었으며 Zygote 내부의 4가지 기능 중 preload구간에서 병렬기법을 적용하였다. preload는 어플리케이션의 구동에 필요한 클래스들과 리소스를 순차적으로 가져오는 함수호출 구조로 이 함수호출 구조를 다른 프로세스로 분리시켜 독립적인 연산을 수행하였다. 제안 방법을 S5PV310 듀얼코어와 Exynos4412 쿼드코어에 적용시켰고 각각 14%와 12%의 성능향상 결과를 보였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.11a
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• pp.1732-1734
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• 2010

멀티 코어 또는 매니 코어 기반의 HPC 시스템 보급이 늘어나면서 HPC 어플리케이션이 사용하는 프로세스의 수 또한 증가하고 있다. 이런 경우, 기존의 IO 방식이 아닌 병렬 IO 의 사용을 고려하여야 하는데 그 중 특히 집합 IO 는 중요한 역할을 수행한다. 본 연구에서는 IBM Power 595 기반 슈퍼 컴퓨터에서 집합 IO 특성을 알아 본다.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.67-69
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• 2020

본 논문은 평면 변압기에서 발생하는 공통모드 노이즈를 제거하기 위해 새로운 회로 구조 및 변압기의 와인딩 레이아웃을 제안한다. 제안하는 컨버터는 1차측의 병렬구조로 인하여 풀-브리지와 같은 구조를 갖고 있고, 높은 파워의 어플리케이션에 적합하게 사용되어질 수 있다. 2개의 하프-브리지 LLC 공진형 컨버터 변압기의 1차측은 한쪽 끝이 정전압 전위를 갖도록 연결되어 있다. 이에 따라 같은 dv/dt 특성을 갖는 1차측과 2차측 와인딩이 존재하게 되고, 이러한 와인딩을 인접하게 배치하는 구조를 통해 변압기에서 발생하는 공통모드 노이즈를 크게 줄일 수 있다. 최종적으로 EMI 필터의 크기를 크게 줄일 수 있고, 높은 전력밀도를 달성할 수 있다.

• Proceedings of the Korean Society of Computer Information Conference
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• 2023.07a
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• pp.561-562
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• 2023

본 연구는 상태관리를 위한 새로운 모델, Quantum State Management (QSM)을 제안한다. QSM은 어플리케이션의 상태를 Quantum이라는 최소 단위로 나누어 비동기 및 병렬처리를 최적화하며, 상태의 추적가능성을 높이는 모델이다. 본 연구에서는 QSM의 개념을 제시하고 이를 Flux 패턴의 Redux와 비교하여 QSM이 갖는 장점과 비교한다.

• Journal of Internet Computing and Services
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• v.18 no.3
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• pp.1-9
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• 2017

Smart Cities intelligently manage numerous infrastructures, including Smart-City IoT devices, and provide a variety of smart-city applications to citizen. In order to provide various information needed for smart-city applications, Smart Cities require a function to intelligently process large-scale streamed big data that are constantly generated from a large number of IoT devices. To provide smart services in Smart-City, the Smart-City Consortium uses stream reasoning. Our stream reasoning requires real-time processing of big data. However, there are limitations associated with real-time processing of large-scale streamed big data in Smart Cities. In this paper, we introduce one of our researches on cloud computing based real-time distributed-parallel-processing to be used in stream-reasoning of IoT big data in Smart Cities. The Smart-City Consortium introduced its previously developed smart-city middleware. In the research for this paper, we made cloud computing based real-time distributed-parallel-processing available in the cloud computing platform of the smart-city middleware developed in the previous research, so that we can perform real-time distributed-parallel-processing with them. This paper introduces a real-time distributed-parallel-processing method and system for stream reasoning with IoT big data transmitted from various sensors of Smart Cities and evaluate the performance of real-time distributed-parallel-processing of the system where the method is implemented.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.3
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• pp.275-287
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• 2000

A virtual reality system must provide participants with a natural interaction, a sufficient immersion, and mostly, realistic images. To achieve this, it is crucial to provide a fast and uniform rendering speed regardless of the complexity of virtual worlds, or the complexity of simulation. In this paper, a virtual reality system which offers an improved rendering performance for complex virtual reality applications has been designed and implemented. The key idea of the proposed system is to exploit the multi-thread scheme in system module design, and execute each modules in parallel. Taking such design approach, rendering, simulation, and interaction can be executed independently. Hence, in applications where a simulation is complex or a scene is very large, this system can provide a more uniform and faster frame rates. The proposed method has been experimented under the various application environments in which scenes and simulations are very complex.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.68-75
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• 2016

As the number of cores and IPs increase in multiprocessor system-on-chip (MPSoC), network-on-chip (NoC) has emerged as a promising novel interconnection architecture for its parallelism and scalability. However, minimization of the latency in NoC with legacy bus IPs must be addressed. In this paper, we focus on the latency minimization problem in NoC which accommodates legacy bus protocol based IPs considering the trade-offs between hop counts and path collisions. To resolve this problem, we propose separated address/data network for independent address and data phases of bus protocol. Compared to Mesh and irregular topologies generated by TopGen, experimental results show that average latency and execution time are reduced by 19.46% and 10.55%, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.89-96
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• 2013

The graphic processor unit (GPU) has been developed to process not only graphic data but also general system data. It shows a better performance than CPU in algorithm for 3D graphics and parallel program. In order to execute algorithm for CPU on GPU, we should understand about GPU architectures and rewrite program considering parallel processing capability and new memory model of GPU. For this reasons, a performance prediction model for the algorithm and its predicted performance through GPU system are required. These can predict problems in GPU application development or construct a performance evaluation standard for GPU. In this paper, we applied the AES encryption algorithms on our performance model and accomplished performance prediction with high accuracy under a heavy workload.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.5_6
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• pp.347-352
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• 2004

This thesis deals with a task scheduling on a message-passing system. Scheduling and allocation are very important issues since the inappropriate scheduling of tasks cannot exploit the true potential of the system and it can offset the grain from parallelization. It is difficult to apply previous schemes to message-passing system, because previous schemes assume the shared memory system. This thesis proposes an modified priority function and processor selection technique that consider the problems caused by the difference between previous models and message-passing environments. The priority function includes the cumulative communication cost which causes task execution to be delayed. The processor selection technique avoids the situation that a child task is assigned to the same Processor allocated to its parent task that has other unscheduled child tasks. We showed by some simulations that our modified features of task scheduling algorithm can make the better scheduling results than the previous algorithms.