• Journal of the Korean Society for Railway
• /
• v.13 no.6
• /
• pp.570-576
• /
• 2010

This paper presents the use of the Petri Net Method for modeling railway tracks. The Petri Net is defined as having the characteristics of a parallel, asynchronous, distributed, inconclusive, statistical, etc. information handling system and is a graphical mathematical modeling tool to study the specifics of active movement. It's proven use can be seen at the Korean type Light Rail testing tracks where they modelled the Petri Net method using the train track encasing the segment, track, turnout, and platform as a singular factor and even though two trains either travelling in the same or opposite directions on a single test track equipped with a sidetrack can travel with the guarantee that the two will not collide.

• Journal of Korea Society of Industrial Information Systems
• /
• v.4 no.4
• /
• pp.88-93
• /
• 1999

Several Iterative methods are considered, Gram-Schmidt algerian for thin orthogonalization and Lanczos methodfor a few extreme eigenvalues. For these methods, a variants of method is derived for which only one synchronization point per on iteration is required; that is one global communication in a message passing distributed-memory machine per one iteration is required The variant is called restructured method, and restructured method has better parallel properties to the conventional method.

• Journal of KIISE:Computing Practices and Letters
• /
• v.6 no.2
• /
• pp.120-134
• /
• 2000

In this paper we present a Distributed Object oriented Virtual computing Environment, called DOVE which consists of autonomous distributed objects interacting with one another via method invocations based on a distributed object model. DOVE appears to a user logically as a single virtual computer for a set of heterogeneous hosts connected by a network as if objects in remote site reside in one virtual computer. By supporting efficient parallelism, heterogeneity, group communication, single global name service and fault-tolerance, it provides a transparent and easy-to-use programming environment for parallel applications. Efficient parallelism is supported by diverse remote method invocation, multiple method invocation for object group, multi-threaded architecture and synchronization schemes. Heterogeneity is achieved by automatic data arshalling and unmarshalling, and an easy-to-use and transparent programming environment is provided by stub and skeleton objects generated by DOVE IDL compiler, object life control and naming service of object manager. Autonomy of distributed objects, multi-layered architecture and decentralized approaches in hierarchical naming service and object management make DOVE more extensible and scalable. Also,fault tolerance is provided by fault detection in object using a timeout mechanism, and fault notification using asynchronous exception handling methods

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.45 no.2
• /
• pp.74-80
• /
• 2008

Spatio-temporal filters are capable of reducing noise from moving pictures, which cannot be dealt with by spatial filters. However, the algorithm is too complicated to be realized as hardware. We implemented a real-time spatio-temporal noise reduction system, using at most three frames, based upon adaptive mean filter algorithm. Some factors which interfere with hardware implementation were modified. Noise estimated from the previous frame was used to filter the current frame so that filtering could be conducted in parallel with noise estimation. This speeds up the system thereby enabling real-time execution. The form of filtering windows was also modified to facilitate synchronization. The proposed structure was implemented on Virtex 4 XC4VLX60, occupying 66% of total slices with 80MHz of the maximum operation frequency.

• Proceedings of the Safety Management and Science Conference
• /
• 1999.11a
• /
• pp.343-343
• /
• 1999

아크용접은 산업전반에 걸쳐 그 생산기반에 없어서는 안될 필수기술로써 자동차 및 조선, 항공우주산업에 이르기까지 경제기반에 미치는 파급효과가 매우 크다. 그러나 이 아크용접을 하게 되면 각종 가스와 미세입자로 이루어진 흄이 발생하게 되는데 이들은 작업자들의 건강에 많은 영향을 미치는 것으로 보고되어 있다. 용접흄에는 용접재료 및 용접공정에 따라 다양한 유해원소가 포함되어 있고 그 종류에 따라 인체에 미치는 잠재적 독성효과도 매우 광범위하다. 최근 국내에서는 용접사들 중에 용접흄에 포함된 중금속 중 Mn중독에 의한 파킨스씨병 환자들과 Cr중독에 의하여 콧속 연골에 구멍이 뚫리는 비중격천공(鼻中隔穿孔) 환자들이 직업병으로 판정 받아 산재요양이 승인된 사례가 있다. 이러한 계기로 인하여 용접사들의 용접기피 현상이 심화되고 작업환경에 대한 법적규제는 선진 외국뿐만 아니라 국내에서도 한층 엄격하게 강화되고 있는 실정이다. 따라서 이제는 작업자와 사용자 모두 용접흄에 대한 인식의 전환이 요구되는 때이며 여러 분야에서 이러한 용접흄에 대한 연구가 활발히 진행되어야 한다. 해외에서는 이미 용접흄에 대한 연구가 활발히 진행되어 왔으나 국내의 경우는 매우 미비한 상태이며 용접산업의 미래 영향력이나 필요성을 고려할 때 국내에서도 적극적인 관심을 가져야 할 부분으로 판단된다. 본 연구에서는 아크용접공정에서 발생하는 흄의 특정 중금속 성분이 인체에 치명적인 악영향을 미치는 것에 착안하여 여러 종류의 용접재료에서 발생되는 용접흄의 중금속 분포를 조사하여 비교하였다. 이것은 향후 용접재료별 및 용접공정별 발생되는 흄의 유해원소를 저감시킬 수 있고 또한 각종 유해원소의 노출기준 및 평가기준을 마련할 수 있는 기초data로써 도움이 되리라 사료된다.동, 공정중재고가 줄어드는 결과를 보였고, 가동률 수준이 높을수록 ORR 방법간의 차이가 크게 나타났다. 그리고 부하평준화 기능은 Order Release 정책의 유효성에 별 영향을 주지 않는 것으로 나타났다. 결론적으로, Order Release 방법은 우선순위규칙간의 성능차이를 줄이거나, 대체할 수 통제 기법이라기보다는 우선순위규칙을 보완하여 공정중재고와 작업현장에서의 리드타임, 리드타임의 편차를 줄여주는 역할을 한다고 볼 수 있다. 그리고, 계획시스템이 존재하여 계획오더가 일정기간간격으로 이송되는 환경에서 특히 유용하다는 결론을 얻었다. 알 수 있었다. 것인데, 제조업에서의 심각한 고비용, 저효율 문제 를 해결하기 위해 필수적으로 도입해야만 하는 실정이다. 또한 소비자의 다양한 요구로 인 하여 제품의 종류와 사양면에서 심한 변동을 보이는 시장 수요에, 신속한 정보처리로 대응 하는데도 크게 기여하고 있다. 이에 본 연구에서는, 자동차 Job Shop의 동기화 생산방식을 지원하는 동기화 생산시스템의 구축 모델을 제시하고자 한다.과로 여겨지며, 또한 혈청중의 ALT, ALP 및 LDH활성을 유의성있게 감소시키므로서 감잎 phenolic compounds가 에탄올에 의한 간세포 손상에 대한 해독 및 보호작용이 있는 것으로 사료된다.반적으로 홍삼 제조시 내공의 발생은 제조공정에서 나타나는 경우가 많으며, 내백의 경우는 홍삼으로 가공되면서 발생하는 경우가 있고, 인삼이 성장될 때 부분적인 영양상태의 불충분이나 기후 등에 따른 영향을 받을 수 있기 때문에 앞으로 이에 대한 많은 연구가 이루어져야할 것으로 판단된다.태에도 불구하고 [-wh]의미의 겹의문사는 병렬적 관계의 합성어가 아니라 내부구조를 지니지 않은 단순한 단어(min

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.37 no.6
• /
• pp.25-34
• /
• 2000

This paper describes design of a 250-Mbps 10-channel optical receiver array for parallel optical interconnection with the general-purpose CMOS technology The optical receiver is one of the most important building blocks to determine performance of the parallel optical interconnection system. The chip in CMOS technology makes it possible to implement the cost-effective system also. Each data channel consists of analog front-end including the integrated photo-detector and amplifier chain, digital block with D-FF and off-chip driver. In addition, the chip includes PLL (Phase-Lock Loop) for synchronous data recovery. The chip was fabricated in a 0.65-${\mu}{\textrm}{m}$ 2-poly, 2-metal CMOS technology. Power dissipation of each channel is 330㎽ for $\pm$2.5V supply.

• The Journal of the Korea Contents Association
• /
• v.9 no.5
• /
• pp.13-23
• /
• 2009

One of the main purpose of multiple-view image processing technology is support realistic 3D image to device user by using multiple viewpoint display devices and compressed data restoration devices. This paper proposes a multiple view image synthesis scheme based on RAM disk which makes possible to browse 3D images generated by applying effective composing method to real time input stereo images. The proposed scheme first converts input images to binary image. We applies edge detection algorithm such as Sobel algorithm and Prewiit algorithm to find edges used to evaluate disparities from images of 4 multi-cameras. In addition, we make use of time interval between hardware trigger and software trigger to solve the synchronization problem which has stated ambiguously in related studies. We use a unique identifier on each snapshot of images for distributed environment. With respect of performance results, the proposed scheme takes 0.67 sec in each binary array. to transfer entire images which contains left and right side with disparity information for high quality 3D image browsing. We conclude that the proposed scheme is suitable for real time 3D applications.

• Journal of KIISE:Computer Systems and Theory
• /
• v.26 no.7
• /
• pp.847-862
• /
• 1999

본 논문에서는 유한버퍼의(finite-buffered) 동기화된(synchronous) 큐잉모델(queueing model)을 이용하여 명령어들간의 병렬성, 분기명령의 빈도수, 분기예측(branch prediction)의 정확도, 캐쉬미스 등의 파라미터들을 고려하여 프로세서의 명령어 실행율을 예측하며 캐쉬의 성능과 파이프라인 성능간의 관계를 분석할 수 있는 새로운 해석적 모델을 제안하였다. 해석적 모델은 모델의 타당성을 검증하기 위해서 시뮬레이션을 수행하여 얻은 결과와 비교하였다. 해석적 모델과 시뮬레이션을 비교한 결과 대부분 10% 오차 내에서 일치하였다. 본 연구를 통하여 얻은 해석적 모델을 사용하면 시뮬레이션에서는 드러나지 않는 성능제약의 원인에 대한 명확한 규명이 가능하기 때문에 성능향상을 위한 설계자료를 얻을 수 있으며, 시스템 성능 밸런스를 위한 캐쉬와 비순차이슈 파이프라인 성능간의 관계에 대한 정확한 분석이 가능하다.Abstract This research presents a novel analytic model to predict the instruction execution rate of superscalar processors using the queuing model with finite-buffer size and synchronous operation mode. The proposed model is also able to analyze the performance relationship between cache and pipeline. The proposed model takes into account various kinds of architectural parameters such as instruction-level parallelism, branch probability, the accuracy of branch prediction, cache miss, and etc.. To prove the correctness of the model, we performed extensive simulations and compared the results with the analytic model. Simulation results showed that the proposed model can estimate the average execution rate accurately within 10% error compared to simulation results. The proposed model can explain the causes of performance bottleneck which cannot be uncovered by the simulation method only. The model is also able to show the effect of the cache miss on the performance of out-of-order issue superscalar processors, which can provide an valuable information in designing a balanced system.

• Journal of KIISE:Databases
• /
• v.28 no.4
• /
• pp.732-741
• /
• 2001

In the relational database systems the join operation is one of the most time-consuming query operations. Many parallel join algorithms have been developed 개 reduce the execution time Multiple hash join algorithm using allocation tree is one of the most efficient ones. However, it may have some delay on the processing each node of allocation tree, which is occurred in tuple-probing phase by the difference between one page reading time of outer relation and the processing time of already read one. This delay problem was solved by using the concept of synchronization of page execution time with we had proposed In this paper the effects of the performance improvements in each node of the allocation tree are extended to the whole allocation tree and the performance evaluation about that is processed. In addition we propose an efficient algorithm for multiple hash joins in limited number of processor environments according to the relationship between the number of input relations in the allocation tree and the number of processors allocated to the tree. Finally. we analyze the performance by building the analytical cost model and verify the validity of it by various performance comparison with previous method.

• The Transactions of the Korea Information Processing Society
• /
• v.2 no.6
• /
• pp.974-984
• /
• 1995

This paper presents a design of a high performance MULVEC (MULtithreaded architecture for the VEctor Computations), as a building block of massively parallel Processing systems. The MULVEC comes from the synthesis of the dataflow model and the extant super sclar RISC microprocesso r. The MULVEC reduces, using status fields, the number of synchronizations in the case of repeated vector computations within the same thread segment, and also reduces the amount of the context switching, network traffic, etc. After be nchmark programs are simulated on the SPARC station 20(super scalar RISC microprocessor)the performance (execution time of programs and the utilization of processors) of MULVEC and the performance(execution time of a program) of *Taccording the different numbers of node are analyzed. We observed that the execution time of the program in MULVEC is faster than that in * T about 1-2 times according the number of nodes and the number of the repetitions of the loop.