• Journal of IKEEE
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• v.23 no.4
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• pp.1288-1294
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• 2019

The channel-achieving property made the polar code show to advantage as an error-correcting code. However, sufficient error-correction performance shows the asymptotic property that is achieved when the length of the code is long. Therefore, efficient architecture is needed to realize the implementation of very-large-scale integration for the case of long input data. Although the most basic fully parallel encoder is intuitive and easy to implement, it is not suitable for long polar codes because of the high hardware complexity. Complementing this, a partially parallel encoder was proposed which has an excellent result in terms of hardware area. Nevertheless, this method has not been completely generalized and has the disadvantage that different architectures appear depending on the hardware designer. In this paper, we propose a hardware design scheme that applies the proposed systematic approach which is optimized for bit-dimension permutations. By applying this solution, it is possible to design a generalized partially parallel encoder for long polar codes with the same intuitive architecture as a fully parallel encoder.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.436-445
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• 2001

In this paper, we introduce modulo ( 2$^n$-1) parallel-processing residue multipliers, using Op Amp circuits, and their technological application to designing binary multipliers. The limit of multiplying speed in computational processing is a serious harrier in the advances of VLSI technology. To solve this problem, we implement a class of modulo ( 2$^n$-1) parallel multipliers having superior time complexity to O( log$_2$( log$_2$( log$_2$$^n$))) by applying Op Amp circuits, while investigating their technological application to binary multipliers. Since they have excellent time & area complexity compared with previous parallel multipliers, and are applicable to designing binary multipliers of the same efficiency, such parallel multipliers possess high academic value. Indexing Terms Modular Multipliers. Binary Multipliers. Parallel Processing, Operational Amplifiers, Mersenne Numbers.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.4 s.316
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• pp.101-108
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• 2007

Parallel processing algorithms, coupled with advanced networking and distributed computing architectures, improve the overall computational performance, dependability, and versatility of a digital signal processing system In this paper, novel parallel algorithms are introduced and investigated for advanced sonar algorithm, conventional matched-field processing (CMFP). Based on a specific domain, each parallel algorithm decomposes the sequential workload in order to obtain scalable parallel speedup. Depending on the processing requirement of the algorithm, the computational performance of the parallel algorithm reveals different characteristics. The high-complexity algorithm, CMFP shows scalable parallel performance on the array of DSP processors. The impact on parallel performance due to workload balancing, communication scheme, algorithm complexity, processor speed, network performance, and testbed configuration is explored.

• Journal of KIISE:Databases
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• v.32 no.5
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• pp.558-566
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• 2005

The XML is the new standard fir data representation and exchange on the Internet. In this paper, we describe a new approach for evaluating a path-oriented query against XML document. In our approach, we propose the Parallel Match Indexing Fabric to speed up evaluation of path-oriented query using path signature and design the parallel match algorithm to perform a match process between a path signature of input query and path signatures of elements stored in the database. To construct a structure of the parallel match indexing, we first make the binary tie for all path signatures on an XML document and then which trie is transformed to the Parallel Match Indexing Fabric. Also we use the Parallel Match Indexing Fabric and a parallel match algorithm for executing a search operation of a path-oriented query. In our proposed approach, Time complexity of the algorithm is proportional to the logarithm of the number of path signatures in the XML document.

• Journal of KIISE:Software and Applications
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• v.35 no.2
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• pp.128-136
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• 2008

Recognition of parallel structure at early stage of sentence parsing can reduce the complexity of parsing. In this paper, we propose an unsupervised language-independent probabilistic model for recongition of parallel noun structures. The proposed model is based on the idea of swapping constituents, which replies the properties of symmetry (two or more identical constituents are repeated) and of reversibility (the order of constituents is inter-changeable) in parallel structures. The non-symmetric patterns that cannot be captured by the general symmetry rule are resolved additionally by the modifier information. In particular this paper shows how the proposed model is applied to recognize Korean parallel noun phrases connected by "wa/kwa" particle. Our model is compared with other models including supervised models and performs better on recongition of parallel noun phrases.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.1_2
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• pp.1-14
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• 2006

Sort-last parallel rendering using a cluster of GPUs has been widely used as an efficient method for visualizing large- scale volume datasets. The performance of this method is constrained by load balancing when data parallelism is included. In previous works static partitioning could lead to self-balance when only task level parallelism is included. In this paper, we present a load balancing scheme that adapts to the characteristic of volume dataset when data parallelism is also employed. We effectively combine the hierarchical data structures (octree and BSP tree) in order to skip empty regions and distribute workload to corresponding rendering nodes. Moreover, we also exploit a 3D clustering method to determine visibility order and save the AGP bandwidths on each rendering node. Experimental results show that our scheme can achieve significant performance gains compared with traditional static load distribution schemes.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.10
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• pp.1919-1926
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• 2016

Because of the enormous processing ability, General-Purpose Graphics Processing Unit(GPGPU) has been applied to many fields including electronics design automation. The SAT algorithm is one of the core algorithm in many electronics design automation tools. There has been some efforts to apply GPGPU to the SAT algorithm, but it is difficult to parallelize the SAT algorithm because of its characteristics. In this paper, I applied GPGPU to the SAT algorithm by parallelizing the propagation routine that is relatively suitable to parallel processing. On the basis of the similarity of the propagation routine to the sparse matrix multiplication, the data structure for the SAT problem is constituted, and the parallel propagation routine is described. To prevent data loss between paralllel threads, atomic operations are exploited. The experimental results for some benchmark SAT problems show that the proposed algorithm is superior to the previous GPGPU-based SAT solver.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.4
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• pp.1-11
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• 1992

A parallel computer "KAPAC(KAIST Parallel Computer)" based on Transputer is designed and implemented. Its purpose is to support the real time processing and high perfomance computing through parallelizing the complex and heavy computation load. KAPAC has UNIX machine as host-computer and is implemented on VME bus as back-end machine. The parallel computer "KAPAC" is the message-passing loosely-coupled multiprocessor computer having thirty two processing elements, and the network topology between processing elements can be easily configured with the crossbar switchs using the control program. Various topologies are introduced and appoication programs are executed on the parallel computer "KAPAC" with eifferent interconnection topologies to show the reconfigurability.to show the reconfigurability.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.11
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• pp.130-138
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• 2016

In this paper present the real-time system parallel testing techniques for weapon systems error verification. Previously field testing equipment in the military field was using the sequential testing method to maintain. This method could not check the error verification of interference. For this reason, in this paper propose the real-time system parallel testing techniques using an embedded module instead of the sequential testing techniques which is used in the weapon system error verification. Using the embedded module mounted switching control card conduct the parallel testing and then send the result to the PC. This method is possible to increase the reliability in the weapon system error verification.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.8
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• pp.863-867
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• 2010

Multi-core processors are becoming increasingly popular. As they are widely adopted in embedded systems as well as desktop PC's, many multimedia applications are being parallelized on multi-core platforms. However, it is difficult to parallelize applications with inherent data dependencies such as encryption algorithms for multimedia data. In order to overcome this limit, we propose a technique to overlap computation and communication using an otherwise idle core in this paper. In particular, we interpret the problem of multimedia computation and communication as a pipeline design problem at the application program level, and derive an optimal number of stages in the pipeline.