• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.3
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• pp.23-32
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• 2001

Since the LILI-128 cipher is a clock-controlled keystream generator, the speed of the keystream data is degraded in a clock-synchronized hardware logic design. Basically, the clock-controlled $LFSR_d$ in the LILI-128 cipher requires a system clock that is 1 ~4 times higher. Therefore, if the same clock is selected, the system throughput of the data rate will be lowered. Accordingly, this paper proposes a 4-bit parallel $LFSR_d$, where each register bit includes four variable data routines for feed feedback of shifting within the $LFSR_d$ . Furthermore, the timing of the propose design is simulated using a $Max^+$plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and the throughput stability is analyzed up to a late of 50 Mbps with a 50MHz system clock. (That is higher than the 73 late at 45 Mbps, plus the maximum delay routine in the proposed design was below 20ns.) Finally, we translate/simulate our FPGA/VHDL design to the Lucent ASIC device( LV160C, 0.13 $\mu\textrm{m}$ CMOS & 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13$\mu\textrm{m}$ semiconductor for the maximum path delay below 1.8ns.

• Korean journal of applied entomology
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• v.59 no.4
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• pp.393-398
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• 2020

The blueberry gall midge, Dasineura oxycoccana (Johnson) (Diptera: Cecidomyiidae), is an emerging pest on cultivated blueberries in Korea. To develop a sensitive tool for monitoring this pest in blueberry orchards, we compared the attractiveness of host plant volatiles and sex pheromone to D. oxycoccana adults. We performed gas chromatography-mass spectrometry (GC-MS) analysis of solid-phase microextraction (SPME)-collected volatiles that were released from blueberry ('Darrow' cultivar). The analysis revealed two major volatiles, cinnamaldehyde and cinnamyl alcohol from flowers; and three major volatiles, β-caryophyllene, germacrene D, and α-farnesene from shoots and young fruits. In field tests conducted in Gunsan, Korea in 2019, commercialized cinnamaldehyde, cinnamyl alcohol, β-caryophyllene, and α-farnesene, used singly or in quaternary combination, were unattractive to the blueberry gall midge. However, traps baited with the known sex pheromone (2R,14R)-2,14-diacetoxyheptadecane attracted significantly more males than the treatments with plant volatiles or the control. No synergistic effect was observed between sex pheromone and plant volatiles. Male D. oxycoccana were captured in the pheromone traps from May to August, with three peaks in mid-May, late June, and late July in Gunsan blueberry fields in 2020.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1627-1634
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• 2021

This paper introduces a low-power compact ADC circuit for analog Convolutional filter for low-power neural network accelerator SOC. While convolutional neural network accelerators can speed up the learning and inference process, they have drawback of consuming excessive power and occupying large chip area due to large number of multiply-and-accumulate operators when implemented in complex digital circuits. To overcome these drawbacks, we implemented an analog convolutional filter that consists of an analog multiply-and-accumulate arithmetic circuit along with an ADC. This paper is focused on the design optimization of a low-power 8bit SAR ADC for the analog convolutional filter accelerator We demonstrate how to minimize the capacitor-array DAC, an important component of SAR ADC, which is three times smaller than the conventional circuit. The proposed ADC has been fabricated in CMOS 65nm process. It achieves an overall size of 1355.7㎛², power consumption of 2.6㎼ at a frequency of 100MHz, SNDR of 44.19 dB, and ENOB of 7.04bit.

• Korean Journal of Optics and Photonics
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• v.35 no.3
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• pp.107-114
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• 2024

In this study, the feasibility of using the covariance-matrix-adaptation-evolution-strategy (CMA-ES) algorithm in a multichannel coherent-beam-combining (CBC) system was experimentally verified. We constructed a multichannel CBC system utilizing a spatial light modulator (SLM) as a multichannel phase-modulator array, along with a coherent light source at 635 nm, implemented the stochastic-parallel-gradient-descent (SPGD) and CMA-ES algorithms on it, and compared their performances. In particular, we evaluated the characteristics of the CMA-ES and SPGD algorithms in the CBC system in both 16-channel rectangular and 19-channel honeycomb formats. The results of the evaluation showed that the performances of the two algorithms were similar on average, under the given conditions; However, it was verified that under the given conditions the CMA-ES algorithm was able to operate with more stable performance than the SPGD algorithm, as the former had less operational variation with the initial phase setting than the latter. It is emphasized that this study is the first proof-of-principle demonstration of the CMA-ES phase-control algorithm in a multichannel CBC system, to the best of our knowledge, and is expected to be useful for future experimental studies of the effects of additional channel-number increments, or external-phase-noise effects, in multichannel CBC systems based on the CMA-ES phase-control algorithm.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.1
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• pp.1-12
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• 2008

In this paper, we present a real-time algorithm for recognizing the vehicle color from the indoor and outdoor vehicle images based on GPU (Graphics Processing Unit) acceleration. In the preprocessing step, we construct feature victors from the sample vehicle images with different colors. Then, we combine the feature vectors for each color and store them as a reference texture that would be used in the GPU. Given an input vehicle image, the CPU constructs its feature Hector, and then the GPU compares it with the sample feature vectors in the reference texture. The similarities between the input feature vector and the sample feature vectors for each color are measured, and then the result is transferred to the CPU to recognize the vehicle color. The output colors are categorized into seven colors that include three achromatic colors: black, silver, and white and four chromatic colors: red, yellow, blue, and green. We construct feature vectors by using the histograms which consist of hue-saturation pairs and hue-intensity pairs. The weight factor is given to the saturation values. Our algorithm shows 94.67% of successful color recognition rate, by using a large number of sample images captured in various environments, by generating feature vectors that distinguish different colors, and by utilizing an appropriate likelihood function. We also accelerate the speed of color recognition by utilizing the parallel computation functionality in the GPU. In the experiments, we constructed a reference texture from 7,168 sample images, where 1,024 images were used for each color. The average time for generating a feature vector is 0.509ms for the $150{\times}113$ resolution image. After the feature vector is constructed, the execution time for GPU-based color recognition is 2.316ms in average, and this is 5.47 times faster than the case when the algorithm is executed in the CPU. Our experiments were limited to the vehicle images only, but our algorithm can be extended to the input images of the general objects.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.1
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• pp.96-110
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• 2017

Most of vehicle detection studies using the existing general lens or wide-angle lens have a blind spot in the rear detection situation, the image is vulnerable to noise and a variety of external environments. In this paper, we propose a method that is detection in harsh external environment with noise, blind spots, etc. First, using a fish-eye lens will help minimize blind spots compared to the wide-angle lens. When angle of the lens is growing because nonlinear radial distortion also increase, calibration was used after initializing and optimizing the distortion constant in order to ensure accuracy. In addition, the original image was analyzed along with calibration to remove fog and calibrate brightness and thereby enable detection even when visibility is obstructed due to light and dark adaptations from foggy situations or sudden changes in illumination. Fog removal generally takes a considerably significant amount of time to calculate. Thus in order to reduce the calculation time, remove the fog used the major fog removal algorithm Dark Channel Prior. While Gamma Correction was used to calibrate brightness, a brightness and contrast evaluation was conducted on the image in order to determine the Gamma Value needed for correction. The evaluation used only a part instead of the entirety of the image in order to reduce the time allotted to calculation. When the brightness and contrast values were calculated, those values were used to decided Gamma value and to correct the entire image. The brightness correction and fog removal were processed in parallel, and the images were registered as a single image to minimize the calculation time needed for all the processes. Then the feature extraction method HOG was used to detect the vehicle in the corrected image. As a result, it took 0.064 seconds per frame to detect the vehicle using image correction as proposed herein, which showed a 7.5% improvement in detection rate compared to the existing vehicle detection method.

• Applied Chemistry for Engineering
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• v.9 no.6
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• pp.870-877
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• 1998

With impedance spectrum measurements, impedance was studied in the interface between sample solutions for $K^+-ion$ selective PVC membrane electrode containing neutral carriers [dibenzo-18-crown-6 (D18Cr6) and valinomycine (Val)]. Response characteristics of electrode were examined by measuring AC impedance spectra that were resulted from the chemical structure and the content of carrier, variation of plasticizer, membrane thickness, doping of base electrolytes, and concentration variation of sample solution. Transport characteristics of PVC membrane electrode were also studied. It was found that the equivalent circuit for the membrane in $K^+$ solution could be expressed by a series combination of solution resistance and a parallel circuit consisting of the bulk resistance and geometric capacitance of the membrane system. But the charge transfer resistance and Warburg resistance were overlapped a little in the low concentration and low frequency ranges. The carrier, D18Cr6 was best for electrode and impedance characteristics, and ideal electrode characteristics were appeared especially in case of doping of the base electrolyte[potassium tetraphenylborate(TPB)]. The optimum carrier content was about 3.23 wt% in case of D18Cr6 and Val. DBP was best as a plasticizer. As membrane thickness decreased the impedance characteristics was improved, but electrode characteristics were lowered for membrane thickness below the optimum. In the case of D18Cr6, the selectivity coefficients by the mixed solution method for the $K^+$ ion were the order of $NH_4{^+}>Ca^{2+}>Mg^{2+}>Na^+$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.19-28
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• 2005

In this paper, we proposed a parallel fast 2-D discrete wavelet transform hardware architecture based on lifting scheme. The proposed architecture improved the 2-D processing speed, and reduced internal memory buffer size. The previous lifting scheme based parallel 2-D wavelet transform architectures were consisted with row direction and column direction modules, which were pair of prediction and update filter module. In 2-D wavelet transform, column direction processing used the row direction results, which were not generated in column direction order but in row direction order, so most hardware architecture need internal buffer memory. The proposed architecture focused on the reducing of the internal memory buffer size and the total calculation time. Reducing the total calculation time, we proposed a 4-way data flow scheduling and memory based parallel hardware architecture. The 4-way data flow scheduling can increase the row direction parallel performance, and reduced the initial latency of starting of the row direction calculation. In this hardware architecture, the internal buffer memory didn't used to store the results of the row direction calculation, while it contained intermediate values of column direction calculation. This method is very effective in column direction processing, because the input data of column direction were not generated in column direction order The proposed architecture was implemented with VHDL and Altera Stratix device. The implementation results showed overall calculation time reduced from $N^2/2+\alpha$ to $N^2/4+\beta$, and internal buffer memory size reduced by around $50\%$ of previous works.

• Journal of Preventive Medicine and Public Health
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• v.21 no.1 s.23
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• pp.21-30
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• 1988

To measure the fertility rate and pregnancy wastage of women in rural area, 3,780 married women under 50 years old who were not sterilized either woman or husband in Gunwee county were followed up for 2 years. Seventeen Myun health workers visited these women periodically to check the status of their family planning practice and menstruation. Pregnant women were interviwed for their past obstetric history and followed up to the time of delivery. Family planning was practiced in 51.6% of the 6,826 women-years observed during the period from April 1, 1985 to March 31, 1987. Pregnancy, abortion and delivery covered 7.6% of the observed women-years and family planning was not practiced in 36.5% of the women-years. When sterilized women at the beginning of the study were included, the family planning practice rate was 72.1% which was slightly higher than the national family planning practice rate. However, 28% of the women of 30-39 years old had not practiced family planning although they had 2-3 children and they used more such less effective methods as safe-period method and condom than the women of 20-29 years old. Overall pregnancy rate was 14.3 per 100 woman-years. Women of 25-29 years old had the highest pregnancy rate of 27.4 per ,100 woman-years. Pregnancy wastage including spontaneous and induced abortions and still births was 22.0% of all pregnancies and it increased with the age of women; 15.8% in women less than 30 years old and 43.7% in women of 30 years and over. Women who terminated the pregnancy with induced abortion had more pregnancies, more previous induced and spontaneous abortions and shorter pregnancy interval than those women who terminated with live birth. Pregnant women terminated with a live birth had received 4.2 prenatal cares on the average. Eighty-five percent of deliveries occurred at a medical facility and 15% at home which was substantially lower home delivery rate than the other rural area of Korea. This may be due to the effects of the demonstration project for the primary health care in 1970s in Gunwee county. These findings suggest that family planning service in rural area should be strengthened by promoting the use of more effective contraceptive method among women over 30 years of age.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.5_6
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• pp.257-266
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• 2007

In On-Chip bus, the arbitration scheme is one of the critical factors that decide the overall system performance. The arbitration scheme used in traditional shared bus is the master-side arbitration based on the request and grant signals between multiple masters and single arbiter. In the case of the master-side arbitration, only one master and one slave can transfer the data at a time. Therefore the throughput of total bus system and the utilization of resources are decreased in the master-side arbitration. However in the slave-side arbitration, there is an arbiter at each slave port and the master just starts a transaction and waits for the slave response to proceed to the next transfer. Thus, the unit of arbitration can be a transaction or a transfer. Besides the throughput of total bus system and the utilization of resources are increased since the multiple masters can simultaneously perform transfers with independent slaves. In this paper, we implement and analyze the arbitration schemes for the Multi-Layer AHB BusMatrix based on the slave-side arbitration. We implement the slave-side arbitration schemes based on fixed priority, round robin and dynamic priority and accomplish the performance simulation to compare and analyze the performance of each arbitration scheme according to the characteristics of the master and slave. With the performance simulation, we observed that when there are few masters on critical path in a bus system, the arbitration scheme based on dynamic priority shows the maximum performance and in other cases, the arbitration scheme based on round robin shows the highest performance. In addition, the arbitration scheme with transaction based multiplexing shows higher performance than the same arbitration scheme with single transfer based switching in an application with frequent accesses to the long latency devices or memories such as SDRAM. The improvements of the arbitration scheme with transaction based multiplexing are 26%, 42% and 51%, respectively when the latency times of SDRAM are 1, 2 and 3 clock cycles.