• Journal of the Korea Knowledge Information Technology Society
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• v.12 no.4
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• pp.539-550
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• 2017

In this paper, we designed, fabricated and tested an UHF band cylindrical dipole array antenna. In the proposed antenna, cylindrical dipoles were vertically arranged in four stages. A parallel structure feeding circuit was installed inside the cylindrical dipole and mounted so as to be broadband matching. The feeding circuit was installed at the center of the cylindrical dipole to optimize the gain flatness characteristic of the azimuth direction omnidirectional radiation pattern. Minimizing the difference between the signals branched from the feeding circuit and realizing the symmetry of the radiation pattern. The required specifications are more than 11.2% bandwidth in UHF band, above 6dBi antenna gain, standing wave ratio of 2:1 or less, less than ${\pm}1dB$ gain flatness in azimuth radiation pattern, more than 13 degrees in elevation radiation pattern of 3dB beamwidth. We confirmed the possibility of implementation through M&S and verified the result of M&S through production and testing. The test results are 11.2% bandwidth in the UHF band, 6.30 to 8.31 dBi gain, 1.53:1 standing wave ratio or less, within ${\pm}0.2dB$ gain flatness in the azimuth radiation pattern, elevation radiation pattern of 3dB beam width was 15.62 to 15.84 degrees. The test result meets all requirements specifications.

• The Journal of the Convergence on Culture Technology
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• v.7 no.1
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• pp.640-645
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• 2021

The deep learning based end-to-end TTS system consists of Text2Mel module that generates spectrogram from text, and vocoder module that synthesizes speech signals from spectrogram. Recently, by applying deep learning technology to the TTS system the intelligibility and naturalness of the synthesized speech is as improved as human vocalization. However, it has the disadvantage that the inference speed for synthesizing speech is very slow compared to the conventional method. The inference speed can be improved by applying the non-autoregressive method which can generate speech samples in parallel independent of previously generated samples. In this paper, we introduce FastSpeech, FastSpeech 2, and FastPitch as Text2Mel technology, and Parallel WaveGAN, Multi-band MelGAN, and WaveGlow as vocoder technology applying non-autoregressive method. And we implement them to verify whether it can be processed in real time. Experimental results show that by the obtained RTF all the presented methods are sufficiently capable of real-time processing. And it can be seen that the size of the learned model is about tens to hundreds of megabytes except WaveGlow, and it can be applied to the embedded environment where the memory is limited.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.26 no.4A
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• pp.647-657
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• 2006

Probabilistic Risk Assessment considering statistically random variables is performed for the preliminary design of a Cable Stayed Bridge, which is Prestressed Concrete Bridge consisted of cable and plate girders, based on the method of Working Stress Design and Strength Design. Component reliabilities of cables and girders have been evaluated using the response surface of the design variables at the selected critical sections based on the maximum shear, positive and negative moment locations. Response Surface Method (RSM) is successfully applied for reliability analyses for this relatively small probability of failure of the complex structure, which is hard to obtain through Monte-Carlo Simulations. or through First Order Second Moment Method that can not easily calculate the derivative terms of implicit limit state functions. For the analysis of system reliability, parallel resistance system consisting of cables and plate girder is changed into series connection system and the result of system reliability of total structure is presented. As a system reliability, the upper and lower probabilities of failure for the structural system have been evaluated and compared with the suggested prediction method for the combination of failure modes. The suggested prediction method for the combination of failure modes reveals the unexpected combinations of element failures in significantly reduced time and efforts compared with the previous permutation method or system reliability analysis method, which calculates upper and lower bound failure probabilities.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.2
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• pp.144-149
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• 2018

The eggs are incubated for 18 days through the generator and incubated in the developing incubator. During the developmental period, the weight loss of the fetus is correlated with the ventricular formation, and the proper ventricular formation is also associated with the healthy embryonic hatching and the egg hatching rate. However, in the incubator period of the domestic hatchery, it is a reality to acquire the resultant side by the Iranian standard weight measurement with the experience of the hatchery and the person concerned and the development period without the apparatus for measuring the present weight. As a result, prevalence of early mortality, hunger and illness during hatching are frequent. Monitoring the reduction of weaning weight is crucial to obtaining chick quality and hatching performance with weight changes within the development machine. Water loss is different depending on the size of eggs, egg shell, and elder group. We can expect to increase the hatching rate by measuring the weight change in real time and optimizing the ventilation change accordingly. There is a need to develop a real-time measurement system that can control 10 to 13% reduction of the total weight during hatching. The system through this study is a way to check the one - time directly when moving the existing egg, and it is impossible to control the measurement of the fetal water evaporation within the development period. Unlike systems that do not affect the hatching rate, four load cells are connected in parallel on the Arduino sketch board and the AT-command command is used to connect the mobile phone and computer in real time. The communication speed of Bluetooth was set to 15200 to match the communication speed of Arduino and Hyper-terminal program. The real - time monitoring system was designed to visually check the change of the weight of the fetus in the artificial incubator. In this way, we aimed to improve the hatching rate and health condition of the hatching eggs.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.1
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• pp.88-95
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• 2002

In recent years, the security of hardware and software systems is one of the most essential factor of our safe network community. As elliptic Curve Cryptosystems proposed by N. Koblitz and V. Miller independently in 1985, require fewer bits for the same security as the existing cryptosystems, for example RSA, there is a net reduction in cost size, and time. In this thesis, we propose an efficient hardware architecture of underlying field arithmetic processor for Elliptic Curve Cryptosystems, and a very useful method for implementing the architecture, especially multiplicative inverse operator over GF$GF (2^m)$ onto FPGA and futhermore VLSI, where the method is based on optimized unit operation components. We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed and inversion speed has been improved 150 times, 480 times respectively compared with the thesis presented by Sarwono Sutikno et al. [7]. The designed underlying arithmetic processor can be also applied for implementing other crypto-processor and various finite field applications.

• Geophysics and Geophysical Exploration
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• v.14 no.1
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• pp.98-104
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• 2011

Numerical simulation in exploration geophysics provides important insights into subsurface wave propagation phenomena. Although elastic wave simulations take longer to compute than acoustic simulations, an elastic simulator can construct more realistic wavefields including shear components. Therefore, it is suitable for exploration of the responses of elastic bodies. To overcome the long duration of the calculations, we use a Graphic Processing Unit (GPU) to accelerate the elastic wave simulation. Because a GPU has many processors and a wide memory bandwidth, we can use it in a parallelised computing architecture. The GPU board used in this study is an NVIDIA Tesla C1060, which has 240 processors and a 102 GB/s memory bandwidth. Despite the availability of a parallel computing architecture (CUDA), developed by NVIDIA, we must optimise the usage of the different types of memory on the GPU device, and the sequence of calculations, to obtain a significant speedup of the computation. In this study, we simulate two- (2D) and threedimensional (3D) elastic wave propagation using the Finite-Difference Time-Domain (FDTD) method on GPUs. In the wave propagation simulation, we adopt the staggered-grid method, which is one of the conventional FD schemes, since this method can achieve sufficient accuracy for use in numerical modelling in geophysics. Our simulator optimises the usage of memory on the GPU device to reduce data access times, and uses faster memory as much as possible. This is a key factor in GPU computing. By using one GPU device and optimising its memory usage, we improved the computation time by more than 14 times in the 2D simulation, and over six times in the 3D simulation, compared with one CPU. Furthermore, by using three GPUs, we succeeded in accelerating the 3D simulation 10 times.

• Journal of Internet Computing and Services
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• v.15 no.3
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• pp.45-52
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• 2014

The Ubiquitous-City (U-City) is a smart or intelligent city to satisfy human beings' desire to enjoy IT services with any device, anytime, anywhere. It is a future city model based on Internet of everything or things (IoE or IoT). It includes a lot of video cameras which are networked together. The networked video cameras support a lot of U-City services as one of the main input data together with sensors. They generate huge amount of video information, real big data for the U-City all the time. It is usually required that the U-City manipulates the big data in real-time. And it is not easy at all. Also, many times, it is required that the accumulated video data are analyzed to detect an event or find a figure among them. It requires a lot of computational power and usually takes a lot of time. Currently we can find researches which try to reduce the processing time of the big video data. Cloud computing can be a good solution to address this matter. There are many cloud computing methodologies which can be used to address the matter. MapReduce is an interesting and attractive methodology for it. It has many advantages and is getting popularity in many areas. Video cameras evolve day by day so that the resolution improves sharply. It leads to the exponential growth of the produced data by the networked video cameras. We are coping with real big data when we have to deal with video image data which are produced by the good quality video cameras. A video surveillance system was not useful until we find the cloud computing. But it is now being widely spread in U-Cities since we find some useful methodologies. Video data are unstructured data thus it is not easy to find a good research result of analyzing the data with MapReduce. This paper presents an analyzing system for the video surveillance system, which is a cloud-computing based video data management system. It is easy to deploy, flexible and reliable. It consists of the video manager, the video monitors, the storage for the video images, the storage client and streaming IN component. The "video monitor" for the video images consists of "video translater" and "protocol manager". The "storage" contains MapReduce analyzer. All components were designed according to the functional requirement of video surveillance system. The "streaming IN" component receives the video data from the networked video cameras and delivers them to the "storage client". It also manages the bottleneck of the network to smooth the data stream. The "storage client" receives the video data from the "streaming IN" component and stores them to the storage. It also helps other components to access the storage. The "video monitor" component transfers the video data by smoothly streaming and manages the protocol. The "video translator" sub-component enables users to manage the resolution, the codec and the frame rate of the video image. The "protocol" sub-component manages the Real Time Streaming Protocol (RTSP) and Real Time Messaging Protocol (RTMP). We use Hadoop Distributed File System(HDFS) for the storage of cloud computing. Hadoop stores the data in HDFS and provides the platform that can process data with simple MapReduce programming model. We suggest our own methodology to analyze the video images using MapReduce in this paper. That is, the workflow of video analysis is presented and detailed explanation is given in this paper. The performance evaluation was experiment and we found that our proposed system worked well. The performance evaluation results are presented in this paper with analysis. With our cluster system, we used compressed $1920{\times}1080(FHD)$ resolution video data, H.264 codec and HDFS as video storage. We measured the processing time according to the number of frame per mapper. Tracing the optimal splitting size of input data and the processing time according to the number of node, we found the linearity of the system performance.

• Journal of the Korea Society of Computer and Information
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• v.17 no.8
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• pp.1-10
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• 2012

This paper proposes design space exploration methodology of many-core processors including multimedia specific instructions to support high-performance and low power ultrasound imaging for portable devices. To explore the impact of multimedia instructions, we compare programs using multimedia instructions and baseline programs with a same many-core processor in terms of execution time, energy efficiency, and area efficiency. Experimental results using a $256{\times}256$ ultrasound image indicate that programs using multimedia instructions achieve 3.16 times of execution time, 8.13 times of energy efficiency, and 3.16 times of area efficiency over the baseline programs, respectively. Likewise, programs using multimedia instructions outperform the baseline programs using a $240{\times}320$ image (2.16 times of execution time, 4.04 times of energy efficiency, 2.16 times of area efficiency) as well as using a $240{\times}400$ image (2.25 times of execution time, 4.34 times of energy efficiency, 2.25 times of area efficiency). In addition, we explore optimal PE architecture of many-core processors including multimedia instructions by varying the number of PEs and memory size.

• Journal of Navigation and Port Research
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• v.38 no.4
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• pp.385-390
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• 2014

Simulator is composed of several devices that have a variety of forms and functions. These devices are connected to each other by a network intricately. For this reason, simulator development and maintenance process require a lot of time and money. In order to successfully develop the simulator, it is ideal that related professionals share the work and work together in parallel. However, development is carried out inefficiently, because task interdependence makes it difficult to work in parallel. In this paper, the developments of the simulator were classified into algorithm development and system development, and it was discussed how to lower the interdependence of these two tasks and support professionals. In particular, based on the requirements analysis of the domain experts responsible for the development of the algorithm, we designed the support tool for simulator development and proposed development process using this tool. We also introduced the concept of a DataSet in order to support algorithm development of domain experts and manage data flexibly. And we designed network architecture to enable flexible reconfiguration of simulator equipment. By using the tools to support the simulator development, domain experts are able to concentrate on algorithm development and it is expected to be effective collaboration. In addition, the development plan and management are expected to be easy because the development process is systematic and clearer.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.11
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• pp.51-62
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• 2003

This paper presents a novel survivor memeory management and decoding techniques with sequential backward state transition control in the trace back Viterbi decoder. The Viterbi algorithm is an maximum likelihood decoding scheme to estimate the likelihood of encoder state for channel error detection and correction. This scheme is applied to a broad range of digital communication such as intersymbol interference removing and channel equalization. In order to achieve the area-efficiency VLSI chip design with high throughput in the Viterbi decoder in which recursive operation is implied, more research is required to obtain a simple systematic parallel ACS architecture and surviver memory management. As a method of solution to the problem, this paper addresses a progressive decoding algorithm with sequential backward state transition control in the trace back Viterbi decoder. Compared to the conventional trace back decoding techniques, the required total memory can be greatly reduced in the proposed method. Furthermore, the proposed method can be implemented with a simple pipelined structure with systolic array type architecture. The implementation of the peripheral logic circuit for the control of memory access is not required, and memory access bandwidth can be reduced Therefore, the proposed method has characteristics of high area-efficiency and low power consumption with high throughput. Finally, the examples of decoding results for the received data with channel noise and application result are provided to evaluate the efficiency of the proposed method.