• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.76-84
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• 2009

This paper proposes a SOC platform which is eligible for education and application SOC design. The platform, fully synthesizable and reconfigurable, includes the OpenRISC embedded processor, some basic peripherals such as GPIO, UART, debug interlace, VGA controller and WISHBONE interconnect. The platform uses a set of development environment such as compiler, assembler, debugger and RTOS that is built for HW/SW system debugging and software development. Designed SOC, IPs and Testbenches are described in the Verilog HDL and verified using commercial logic simulator, GNU SW development tool kits and the FPGA. Finally, a multimedia SOC derived from the SOC platform is implemented to ASIC using the Magnachip cell library based on 0.18um 1-poly 6-metal technology.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.8
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• pp.1181-1186
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• 2002

This system is controlled by PC application programs through USB interface. PC application programs make image files, user's files , sound files and option files. And these files are downloaded to external memory card of this system. The other PC application programs monitor status of DARC, GPS, LED module of this system. The PC application programs help user manage this system efficiently.

• The Transactions of the Korea Information Processing Society
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• v.3 no.5
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• pp.1229-1239
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• 1996

The increase of additional information broadcasting of TV demands a graphic overlay processor. This paper is about the design, implementation and testing of a graphic overlay processor called by KBPS decoder ASSP (Applicatio n Specific Standard Product) which is compliance with Korea Broadcast Programming System. KBPS decoder ASSP consists of embedded 8 bit microprocessor Z80, graphic overlay controller, KBPS schedule decoder, memory controller, priority interrupt controller, MIDI controller, infrared raccoon receiver, async scrial communication controller, timer, bus controller, universal parallel input-output port and serial-parallel interface. The 0.8 micron CMOS Sea of Gate is used to implement the ASSP in amount of about 31,500 gates, and it is running at 14.318MHz.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.4
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• pp.41-49
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• 2004

In this paper, a design and measurement method for FPGA embedded gigabit-transceiver is presented. Altera's Stratix GX device which is general purpose transceiver called GXB was used for implementing PCI Express transceiver. PCI Express is the generation high performance serial I/O bus used to interconnect peripheral devices. After GXB was set follow by PCI Express specifications, the design has been verified by timing simulation and implemented as hardware. We tested it as follow. First GXB internal digital and analog block test second GXB transmitter signal integrity test called Eye mask test, third GXB high-speed serial I/O buffer and on-chip termination test and the last GXB protocol test. This paper shows all the design and measurement procedure about FPGA embedded gigabit-transceiver.

• Journal of the Korea Society of Computer and Information
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• v.25 no.6
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• pp.1-8
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• 2020

Communication between system modules is applied using the Modbus protocol in industrial sites including smart factories, industrial drones, building energy management systems, PLCs, ships, trains, and airplanes. The existing Modbus was used for serial communication, but the recent Modbus protocol is used for TCP/IP communication.The Modbus protocol supports RTU, TCP and ASCII, and implements and uses protocols in embedded systems. However, the transmission I/O devices for RTU, TCP, and ASCII-based protocols may differ. For example, RTU and ASCII communications transmit on a serial-based communication protocol, but in some cases, Ethernet TCP/IP transmission is required. In particular, since the C language (object-oriented) is used in embedded systems, the complexity of source code related to I/O registers increases. In this study, we designed software that can logically separate I/O functions from embedded devices, and designed the execution logic of each instance requiring I/O processing through a delegate class instance with Modbus RTU, TCP, and ASCII protocol generation. We designed and experimented with software that can separate communication I/O processing and logical execution logic for each instance.