• Title/Summary/Keyword: 버스 시뮬레이션

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Development of Determining Technique of Optimum Signal Time of Intersections On Median Exclusive Bus Lane using Bus-only Signal (중앙버스전용차로 버스전용신호 도입시 신호 최적화에 관한 연구)

  • Kim, Bo-Gyeom;Kim, Seung-Il;Kim, Yeong-Chan;Kim, Jin-Tae
    • Journal of Korean Society of Transportation
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    • v.24 no.5 s.91
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    • pp.123-133
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    • 2006
  • Seoul and many large cities in Korea have implemented Median Exclusive Bus Lane(MEB). But exclusive bus lane in the middle of the road caused new contradictions between left turn movement and through bus movement and several signal operation techniques like 'left turn Protected' and 'overlap phase' couldn't be applied in intersections on MEB. We suggest 'Bus-only Signal for median lane technique as solution of these problems This study presents optimum signal time design process and detailed algorithms for intersections where bus-only signals are installed. As a test field. we took Yang-Je intersection where Median Exclusive Bus Lane go through. and have large gap in volume of left turn in main direction. And we verified that revised optimum signal time including overlap phase can reduce average delay time of vehicle through before and after simulation.

A Study of decoration simulation using Metaverse (메타버스를 활용한 꾸미기 시뮬레이션 연구)

  • Kwang-Hyuk Im;Min-ji Kim;Su-Ah Lee;Ye-Ram Lee;Seok-Hun Kim
    • Proceedings of the Korean Society of Computer Information Conference
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    • 2023.01a
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    • pp.297-298
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    • 2023
  • 팬덤 문화가 확산함에 따라 굿즈 구매량이 증가하였고, 동시에 포토카드를 탑로더에 넣어 꾸미는 '탑꾸'를 SNS에 자랑하는 문화가 형성되었다. 그러나 구매 전 꾸미기 재료를 미리 조합해 볼 수 없어 실제로 재료를 조합할 때 비용적, 시간적, 자원 소모 측면에서 문제점이 발생하고 있다. 현재 가상 세계가 발전하면서 현실에서 실현하기 어려웠던 것을 시도할 수 있게 되었고, 소비자들도 가상 세계에서 활발하게 교류하고 있다. 본 논문에서는 '메타버스를 활용한 꾸미기 시뮬레이션'을 개발하여 탑로더를 꾸밀 때 발생하는 시행착오를 줄이고 비용을 절감할 방안을 제시한다.

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Metaverse R&D Promotion Strategy Reflecting Digital Ethics and UX (디지털 윤리와 UX를 반영한 메타버스 R&D 추진전략)

  • Bang, Junseong;Park, Pangun
    • Journal of Broadcast Engineering
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    • v.27 no.5
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    • pp.703-717
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    • 2022
  • Metaverse provides a simulated environment that can produce various values while conducting economic, social, and cultural activities in a digital society where the virtual and real worlds are connected. In this paper, the direction of technological progress is predicted by analyzing the characteristics of Metaverse services and their businesses. Technologies and latest researches for the realization of the Metaverse service platform are also explored. In addition, Metaverse Ethics to construct a sustainable Metaverse and Metaverse UX to increase users' service participation are also discussed. Moreover, the R&D promotion strategy for Metaverse services are presented.

Performance Analysis of Bandwidth-Awared Bus Arbitration Method (점유율을 고려한 버스 중재방식의 성능 분석)

  • Lee, Kook-Pyo;Koh, Si-Young
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.9
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    • pp.2078-2082
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    • 2010
  • The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. Conventional arbitration method is considered bus priority primarily, actual bus utilization didn't considered. In this paper, we propose arbitration method using bus utilization operating block of each master, we verify the performance compared with the other arbitration methods through throughput performance. From the result of performance verification, we confirm that proposed arbitration method, matched bus utilization set by the user 40%, 20%, 20%, 20%.

Bus Splitting Techniques for MPSoC to Reduce Bus Energy (MPSoC 플랫폼의 버스 에너지 절감을 위한 버스 분할 기법)

  • Chung Chun-Mok;Kim Jin-Hyo;Kim Ji-Hong
    • Journal of KIISE:Computer Systems and Theory
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    • v.33 no.9
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    • pp.699-708
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    • 2006
  • Bus splitting technique reduces bus energy by placing modules with frequent communications closely and using necessary bus segments in communications. But, previous bus splitting techniques can not be used in MPSoC platform, because it uses cache coherency protocol and all processors should be able to see the bus transactions. In this paper, we propose a bus splitting technique for MPSoC platform to reduce bus energy. The proposed technique divides a bus into several bus segments, some for private memory and others for shared memory. So, it minimizes the bus energy consumed in private memory accesses without producing cache coherency problem. We also propose a task allocation technique considering cache coherency protocol. It allocates tasks into processors according to the numbers of bus transactions and cache coherence protocol, and reduces the bus energy consumption during shared memory references. The experimental results from simulations say the bus splitting technique reduces maximal 83% of the bus energy consumption by private memory accesses. Also they show the task allocation technique reduces maximal 30% of bus energy consumed in shared memory references. We can expect the bus splitting technique and the task allocation technique can be used in multiprocessor platforms to reduce bus energy without interference with cache coherency protocol.

Regional voltage control using pilot bus (Pilot bus를 이용한 지역별 전압 제어)

  • Lee, Ho-Chul;Song, Sung-Hwan;Kim, Sun-Kyo;Yoon, Yong-Tae;Moon, Seung-Il
    • Proceedings of the KIEE Conference
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    • 2006.07a
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    • pp.210-211
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    • 2006
  • 본 논문은 무효전력 특성에 따라 나누어진 각 지역의 대표 pilot bus 전압을 기준으로 계통 전압을 제어함으로 계통 내에 모든 버스 전압을 통한 제어보다 효율적인 방법을 제시한다. Pilot bus 전압을 기준으로 하는 경우는 계통내 모든 버스의 전압을 기준으로 하는 경우에 비해 필요로 하는 정보의 양이 작을 것이므로 더 효율적이라고 할 수 있다. 본 논문에서는 IEEE 14 버스 시스템에서 특정 상정사고가 일어났을 경우를 가정으로 steady state voltage monitoring and control(SSVMC)를 통한 전압제어 시뮬레이션을 하였다. 모든 버스 전압을 기준으로 한 경우와 pilot bus 전압을 기준으로 SSVMC해준 경우를 비교 제시하였다.

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TFT-LCD Controller Implementation Using DMA of High Performance in Multi-Bus Architecture (다중버스 아키텍처 구조에서 고성능 DMA를 이용한 TFT-LCD Controller 구현)

  • Lee, Kook-Pyo;Lee, Keun-Hwan;Yoon, Yung-Sup
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.8
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    • pp.54-60
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    • 2008
  • The bus architecture consists of a master initiating a communication transaction, a slave responding to the transaction, a arbiter selecting a master, a bridge connecting buses and so on. Recently this is more complicated and developed toward multi-bus architecture. In this paper, several cases of multi-shared bus architecture are discussed and in order to decrease the bridge latency, the architecture introducing a memory selector is proposed. Finally, a LCD controller using DMA master is integrated in this bus architecture that is verified due to RTL simulation and FPGA board test. DMA, LCD line buffer and SDRAM controller are normally operated in the timing simulation using ModelSim tool, and the LCD image is confirmed in the real FPGA board containing LCD panel.

Analyzing the Changes in Speed Due to High Occupancy Vehicles Using Median Bus Lane (다인승차량의 중앙버스전용차로 이용에 따른 영향분석)

  • Lee, Jung-Beom
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.12 no.4
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    • pp.87-94
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    • 2013
  • This study estimated the changes in delays and speeds of vehicles in exclusive bus lane and road when the High Occupancy Vehicles(HOV) use the median bus lane. Synchro simulation tool was used to optimize the traffic signal time on the network and VISSIM was applied to simulate various scenarios. Here, drivers behavior parameters in VISSIM was optimized using Simultaneous Perturbation Stochastic Approximation(SPSA) algorithm in order to represent real traffic condition. Based on the simulation results, the delay in Doan daero was decreased when the volume of HOV in current condition runs on the median bus lane, whereas delay in Doan dongro was increased in all scenarios. The changes in bus speed was not sharply decreased for both study sites, even though the number of HOV increased to 10%. Thus, it could be allowed that the HOV use the median bus lane in Doan dongro and Doan daero. Future research tasks include studying about changes in delay when the HOV use the curb bus lane.

System Dynamics Interpretation on Bus Scheduling Model (시스템 다이나믹스 관점에서의 버스 운영계획모형 해석)

  • Kim, Kyeong-Sik
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.8 no.1
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    • pp.1-8
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    • 2009
  • This paper aims mainly to reinterpretate Optimal Bus Scheduling Model by applying System Dynamics Perspective. Traditionally, the study regarding Optimal Bus Scheduling Model stems on the linear relationshp. However, this paper attempted to convert linear relationship based Optimal Bus Scheduling Model to causal loop perspective based Model. In result, the paper present Casual Loop Diagram for Optimal Bus Scheduling Model. Furthermore, the paper also ran a simulation based on Stock & Flow Diagram for Optimal Bus Scheduling Model. The outcome was not much different from the linear relationship based Model due to the similarity of the equation applied on two models.

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Development of Shock Wave Delay Estimation Model for Mixed Traffic at Unsaturated Signalized Intersection (충격파를 이용한 신호교차로 지체산정 모형 개발 (비포화 2차로 신호교차로 상에서의 버스혼합교통류 지체산정모형))

  • Kim, Won-Gyu;Kim, Byeong-Jong;Park, Myeong-Gyu
    • Journal of Korean Society of Transportation
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    • v.28 no.6
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    • pp.75-84
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    • 2010
  • Controlled traffic intersection is critical point in terms of transportation network performance, where the most of traffic congestion arises. One of the most important and favorable measure of effectiveness in the signal controlled intersection is approach delay. Although lots of efforts to develop traffic delay estimation models have been made throughout the years, most of them were focusing on homogeneous traffic flow. The purpose of this research is to develop a traffic delay estimation model for traffic flow mixed with bus based on the horizontal shockwave theory. Traffic simulation is performed to test the adaptation level of the model in generic environment. The result shows that the delay increases with increasing bus traffic. Overall model accuracy comparing simulation result is acceptable, that shows the error range around 10 percent.