• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2010.07a
• /
• pp.287-290
• /
• 2010

최근 기기간의 접속에 적합한 근거리 무선 접속기술의 요구가 증대됨에 따라, 그 요구에 대응하는 무선통신기술의 하나로 UWB(Ultra Wide Band)가 주목을 받고 있다. 특히, TV와 캠코더, 카메라 등의 AV기기 상호 간의 무선접속을 포함하여 PC나 휴대정보단말(PDA) 등이 네트워크에 무선으로 접속하는데 UWB 기술은 주요한 역할을 담당할 것으로 예상된다. 최근 서비스가 진행되고 있는 HDTV를 비롯하여 향후 UHDTV(Ultra-HDTV) 등의 방송시스템이 본격화되면 HD급 이상의 캠코더는 고해상도에 따른 대용량 데이터를 저장하고 AV기기 간의 데이터 전송을 위해 고속 무선 데이터 전송이 필수적이다. 또한 이와 같은 고속 무선데이터 전송을 위해서는 보다 안정된 송수신 기술이 절대적으로 필요하다. 이를 위하여 본 논문에서는 차세대 UWB의 설계 제약조건 중 하나인 저전력 송신환경에서 수신 신뢰도의 향상을 이루기 위해 LDPC code를 오류정정부호로 고려하고, 제한된 반복복호 횟수를 가지고 개선된 성능을 얻기 위해 새로운 복호 알고리즘을 제안하였다. 또한, 제안한 복호 알고리즘에 대해 모의실험을 통하여 성능을 검증함으로써 차세대 UWB 송수신 기술로서의 유용성과 적용 가능성을 제시하였다.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.14 no.5
• /
• pp.583-586
• /
• 2004

Transition jitter noise is one of major sources of detection errors in high density recording channels. Implementation complexity of the optimal detector for such channels is high due to the data dependency and correlated nature of the jitter noise. In this paper, two types of hardware efficient sub-optimal detectors are derived by modifying branch metric of Viterbi algorithm and applied to partial response (PR) channels combined with run length limited modulation coding. The additional complexity over the conventional Viterbi algorithm to incorporate the modified branch metric is either a multiplication or an addition for each branch metric in the Viterbi trellis.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2014.11a
• /
• pp.15-17
• /
• 2014

본 논문에서는 하드웨어의 제한된 자원을 이용하여 HEVC 코덱을 구현할 때 DCT 와 엔트로피 부호화를 사용하지 않고 율 및 왜곡값을 예측하여 고효율의 부호화를 수행하는 방법에 대하여 제안한다. HEVC 는 기존의 부호화기에 비하여 계층적 부호화 구조와 함께 큰 블록 크기를 갖는 DCT 와 엔트로피 부호화를 반복적으로 수행하기 때문에 하드웨어 구현 시 그 복잡도가 매우 크게 증가한다. 먼저 DCT 는 하다마드변환 행렬과 또 다른 정규 직교 변환 행렬의 곱으로 표현될 수 있는 성질을 이용하여 부호화 변환 시 생성된 하드마드변환 행렬에 저복잡도의 정규 직교 변환 행렬을 곱하여 DCT 변환 계수를 생성한 후 변환 및 양자화를 수행한다. 왜곡값의 경우, 이 때 생성된 양자화 계수와 변환 계수 간의 차이를 변환도메인에서 제곱합을 이용하여 계산하여 역변환을 생략함으로써 복잡도를 감소시킬 수 있다. 또한 텍스처에 대한 비트율 예측은 각 CU 블록내의 양자화 계수의 수를 더하여 계산하여 엔트로피를 수행하지 않고 예측할 수 있다. 그리고 비 텍스처에 대한 비트율 예측의 경우 움직임벡터의 비트에 대한 Pseudo CABAC 코드를 수행하여 예측할 수 있다. 이러한 저 복잡도의 텍스처 및 비텍스처 비트와 왜곡을 예측함으로써 하다마드변환만을 이용하여 부호화하였을 때에 비해 최대 33%의 비트율 감소를 얻을 수 있었다.

• Journal of Advanced Marine Engineering and Technology
• /
• v.40 no.6
• /
• pp.535-541
• /
• 2016

In this paper, we analyzed efficient decoding scheme with FTN(Faster than Nyquist) method that is transmission method faster than Nyquist theory and increase the throughput. Applying the FTN method to satellite and underwater communication, we proposed an efficient transceiver model. To minimize ISI(Inter-Symbol Interference) induced by FTN signal, turbo equalization algorithms that iteratively exchange probabilistic information between Viterbi equalizer based on BCJR algorithm and LDPC decoder are used in satellite communication. In others, for underwater communication, DFE equalizer and LDPC decoder are concatenated to improve performance.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.11A
• /
• pp.1682-1690
• /
• 2000

최근들어 초광대역 시간 도약 임펄스 무선 전송(ultra wideband time hopping impulse radio; 이하 IR) 기술이 실내 무선 LAN이나 군용 무선 통신 시스템 등을위한 새로운대역 확산 전송 방식으로서 큰 관심을 모으고 있다 IR 시스템은 1(nsec) 이하의 매우 짧은 펄스폭의 펄스 위치 변조(pulse position modulation)된 가우시안 모노사이클 펄스열을 이용함으로서 매우작은 크기 의수 GHz에 이르는 초광대역 스펙트럼을 가지며 기존의 통신 시스템에 거의 간섭을 미치지 않으면서 사용 가능하다. 본 논문에서는 IR 시스템에 M진 (M-ary) PPM 방식을 적용하는 경우의 성능을 평가하였다. 특시 의사 잡음 부호 발생기와 10진 변환기(decimator)로 구성된 시간 도약 패턴을 사용하여 다원 접속 간섭이 배제되는 부가성 백색 가우시안 잡음 채널 하의 동기식(synchronous) IR 시스템에서, 심벌 수, M, 가우시안 모노사이클 펄스 폭 $\tau$$_{p}$, PPM에서 펄스 간 간격$\delta$, 펄스 반복 횟수 N$_{s}$ 등과 같은 다양한 시스템 파라미터의 조합에 따른 성능 변화를 모의 실험을 통해 확인하였으며, 이러한 결과를 통해 비트 오율, 시스템 복잡도 및 전송율 등의 사양에 따라 적합한 M 진 PPM IR 시스템의 구성 방안에 대한 근거를 제공하였다.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.14 no.5
• /
• pp.805-810
• /
• 2019

Recently, a majority of 4G mobile telecommunication manufacturers prefer repeaters with good adaptability. In this paper, we propose a new LMF(: Least Means Fourth) algorithm for LTE(: Long Term Evolution) RF(: Radio Frequency) Repeater. The proposed algorithm is a modification of the LMF, which appropriately adjusts the step size and improves performance according to the Sign function. The steady state MSE(: Mean Square Error) performance of the proposed LMF algorithm with step size of 0.009 is low level at about -25dB, and the proposed LMF algorithm requires 500 less iterations than the conventional algorithms at MSE of -25dB.

• Journal of Korea Multimedia Society
• /
• v.11 no.10
• /
• pp.1359-1365
• /
• 2008

The portion of header in H.264 gets higher than those of previous standards instead of its better compression efficiency. Therefore, this paper proposes a new technique to compress the header of H.264. Unifying a sentence elementary in H.264, H.264 does not consider the distribution of element which be encoded and uses existing Exp-Golomb method, but it is uneffective for variable length coding. Most of the header are block type(s) and motion vector difference(s), and there are redundancies in the header of H.264. The redundancies in the header of H.264 which are analyzed in this paper are three. There are frequently appearing symbols and non-frequently appearing symbols in block types. And when mode 8 is selected in macroblock, all of four sub-macroblock types are transferred. At last, same values come in motion vector difference, especially '0.' This paper proposes the algorithm using type code and quadtree, and with them presents the redundant information of header in H.264. The type code indicates shape of the macroblock and the quadtree does the tree structured motion compensation. Experimental results show that proposed algorithm achieves lower total number of encoded bits over JM12.4 up to 32.51% bit reduction.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.1A
• /
• pp.26-34
• /
• 2002

Mobile telecommunication systems such as IS-95 and IMT-2000 employ frame based communication using frames up to 20 msec in length and the receiving end has to store the whole frome before it is being processed. The size of the frame buffer ofter dominates those of the processing unit such as soft decision Viterbi decoder. The frame buffer for IMT-2000, for example, has to be increased 80 times as large as that of IS-95. One of the parameters deciding the number of bits in a frame will be obviously the number of bits in soft quantization. Start after striking space key 2 times. This paper has studied a new aspect of offset and quantization step size on BER performance and proposes a new 3-bit soft quantization algorithm which shows similar performance as that of 4-bit soft decision Viterbi receiver. The optimal offset values and step sizes for the other practical quantization levels ---16, 8, 4, 2--- have also been found. In addition, a new optimal symbol metric table has been devised which takes the accumulation value of various repeated signals and produces a rescaled 3-bit valu.tart after striking space key 2 times.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.7
• /
• pp.97-103
• /
• 2004

In this paper, we propose a high speed block turbo code decoding algorithm and an efficient hardware architecture. The multimedia wireless data communication systems need channel codes which have the high-performance error correcting capabilities. Block turbo codes support variable code rates and packet sizes, and show a high performance due to a soft decision iteration decoding of turbo codes. However, block turbo codes have a long decoding time because of the iteration decoding and a complicated extrinsic information operation. The proposed algorithm using the threshold that represents a channel information reduces the long decoding time. After the threshold is decided by a simulation result, the proposed algorithm eliminates the calculation for the bits which have a good channel information and assigns a high reliability value to the bits. The threshold is decided by the absolute mean and the standard deviation of a LLR(Log Likelihood Ratio) in consideration that the LLR distribution is a gaussian one. Also, the proposed algorithm assigns '1', the highest reliable value, to those bits. The hardware design result using verilog HDL reduces a decoding time about 30% in comparison with conventional algorithm, and includes about 20K logic gate and 32Kbit memory sizes.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.1
• /
• pp.20-27
• /
• 2010

This paper describes a design of 5-stage pipelined de-blocking filter with power reduction scheme and proposes a efficient memory architecture and filter order for high performance H.264/AVC Decoder. Generally the de-blocking filter removes block boundary artifacts and enhances image quality. Nevertheless filter has a few disadvantage that it requires a number of memory access and iterated operations because of filter operation for 4 time to one edge. So this paper proposes a optimized filter ordering and efficient hardware architecture for the reduction of memory access and total filter cycles. In proposed filter parallel processing is available because of structured 5-stage pipeline consisted of memory read, threshold decider, pre-calculation, filter operation and write back. Also it can reduce power consumption because it uses a clock gating scheme which disable unnecessary clock switching. Besides total number of filtering cycle is decreased by new filter order. The proposed filter is designed with Verilog-HDL and functionally verified with the whole H.264/AVC decoder using the Modelsim 6.2g simulator. Input vectors are QCIF images generated by JM9.4 standard encoder software. As a result of experiment, it shows that the filter can make about 20% total filter cycles reduction and it requires small transposition buffer size.