• Journal of the Semiconductor & Display Technology
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• v.23 no.1
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• pp.25-35
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• 2024

In the present modern day, as the complexity and size of SoC(System on Chip) increase, the importance of design verification are increasing, Therefore it takes a lot of time to verify the design. There is an emerging need to manage the verification environment faster and more efficiently by reusing the existing verification environment. UVM-based verification is a standardized and highly reliable verification method widely adopted and used in the semiconductor industry. This paper presents a UVM-based verification for the 4 tap equalizer module with a systolic array structure. Through the constraints randomization, it was confirmed that various test scenarios stimulus were generated. In addition, by verifying a simulation comparing the actual DUT outputs with the MATLAB reference outputs, the reuse and efficiency of the UVM test bench could be confirmed.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.4
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• pp.1210-1215
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• 2010

The probe card are test modules which are to classify the good semiconductor chips and thin film before the packaging process. In the rapid growth a technology of semiconductor, the number of pads per unit area is increasing and pad arrays are becoming irregular. Therefore, the technology of probe card needs narrow width and lots of probe tip. In this paper, the probe tip based on the MEMS(Micro Electro Mechanical System)technology was developed a new MEMS probe tip for vertical probe card applications. For the structural designs of probe tip were performed to mechanical characteristics and structural analysis using FEM(Finite Element Method). Also, the contact force of MEMS probe tip compared with FEM results and experimental results. Finally, the MEMS probe card was developed a fine pitch smaller than $50{\mu}m$.

• The Journal of Korean Institute for Practical Engineering Education
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• v.1 no.1
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• pp.30-37
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• 2009

The purpose of this study is the development and application of practical education program for the security of semiconductor equipments maintenance technology. For securing the semiconductor equipments maintenance technology, this study aims to research on the Training and Development. The main field of HRD is about the Training and Development. We develop the practical education program applying the ADDIE Model to conduct the education training. This developed program tests the education training on the officers of Samsung Electronics, the maker of semiconductor. By the test, we hope to provide the technology education program focusing on the practical experiences of systematic and effective companies.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.37 no.4
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• pp.205-213
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• 1988

It has been very difficult to solve the semiconductor problems by numerical analysis techique due to the strong nonlinearity of the governing equations. Thus, we proposed a double structured adaptive refinement scheme to the finite element analysis of semiconductor devices, which guarantees a succesive convergency and gives better quality to the solutions.i.e., in the first step, the main factor of divergence in the current continuity equation is eliminated and the next, the solution quality is improved by reducing the discontinuity of current. The result of test application to the GaAs MESFET model shows that the proposed method is much dffective and efficient in the numerical analysis of semiconductor.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.338-338
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• 2010

공정 중 발생하는 입자는 반도체 생산 수율에 가장 큰 영향을 끼치는 원인으로 파악되며, 생산 수율을 저하시키는 원인 중 70% 가량이 이와 관련된 것으로 알려져 있다. 현재 반도체 공정에서 입자를 계측하는데 사용하는 PWP (Particle per Wafer Pass) 방법은 표준 측정방법으로 널리 쓰이고 있으나, 실시간으로 입자의 양을 측정할 수 없고, Test wafer 사용에 따른 비용증가의 단점이 있어 공정 중에 입자를 실시간으로 측정할 수 있는 대안기술이 필요한 실정이다. ISPM (In-Situ Particle Monitoring)은 레이저 산란방식을 이용한 실시간 입자측정 장비로서 오염원 발생에 대한 즉각적인 대처와 조치가 가능하고 부가적인 추가 비용이 발생하지 않기 때문에 실시간 모니터링 장비가 없는 현재의 반도체 공정에 충분히 적용될 가능성이 있다. 특히 CVD 공정은 반도체 공정의 약 30%를 차지할 만큼 중요한 단계로 생성되는 오염입자 모니터링을 통해 공정 불량 유무를 판단할 수 있을 것으로 기대된다. 본 연구에서는 Silane 가스를 이용한 PECVD (Plasma Enhanced Chemical Vapor Deposition) 공정 중 발생되는 오염입자를 ISPM을 이용하여 실시간으로 측정하였다. 챔버 배기구에 두 가지 타입의 ISPM을 설치하고 공정압력, 유량, 플라즈마 파워를 공정변수로 하여 각각의 조건에서 발생되는 오염입자의 분포 변화를 실시간으로 측정하였으며 결과를 비교 분석하였다.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.77-80
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• 1997

In this paper presented is a temperature controller for a semiconductor test handler. Using ARMAX model and least square method, the chamber model for the design of a controller is identified through experiment. With the identified model an LQG/LTR controller is designed. Experiment with a real test handler demonstrated good performance in that its overshoot is small and response time is fast.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.8
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• pp.4815-4820
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• 2014

As semiconductor chips are on a small scale, large content and high integratation, it is essential to develop the device of pick and place at the system of the semiconductor test handler to ensure its high precision and durability. In this study, inspection equipment frame model of a semiconductor test handler picker was investigated by vibration analysis with the property of the natural frequency and harmonic response. As 3 kinds of analysis case models, the device of pick and place was located at the left side (Case 1), the center (Case 2) and the right side (Case 3) of the upper guideline. The range of natural frequencies until the 6th order on this frame model ranges from 80Hz to 500Hz. As the analysis of the harmonic response when the frame is resonant, Case 2 showed the maximum equivalent stress of 52.802 MPa more than Cases 1 or 3. Case 2 was the most intensive among the three cases. Using the analysis result of this study, the design of the frame model, which can be applied to the safe working environment of the system is believed to be possible.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.1
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• pp.51-63
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• 1993

"Algorithm DA" is proposed to test linked 2-CFs(2-Coupling Faults) with order 2 or 3 which are not perfectly detected in conventional algorithms. "Test 1*", "Test 2*" and "Algorithm RA" are proposed restricted 3-CFS. The time complexity of "Test 1*" is reduced in view of the detection of 3-CFS. "Test 2*" and "Algorithm RA" have not only the reduces time complexity but also the improved fault coverage in comparison with conventional algorithms. And "Algorithm RA" can be applied step by step according to the degree of the fault coverage. If "Algorithm RA" is applied to the memory with parallel test. its time complexity is reduced considerably. It is proved that the MT(March Test) with nonlinear address sequences can not detect perfectly the CFs more complex than linked 2-CFs with order 3.ss sequences can not detect perfectly the CFs more complex than linked 2-CFs with order 3.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.05a
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• pp.811-812
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• 2012

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.73-76
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• 1997

The temperature control system for semiconductor test handler is designed. We controlled the temperature of chamber using 3-wire RTD sensor and MVME EMbedded controller. VxWorks that is a real-time operating system is used and heater is controlled by PWM. Temperature fluctuation of chamber is decreased within 0.3.deg. C, which is about one-half of that of commercial controller.