• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.05a
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• pp.51-54
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• 2003

반도체 산업의 발전에 따라 생산과정에서의 반도체 소자의 특성을 검사하고, 오류를 검출하는 작업을 효율성 있게 하여 생산성을 향상시키는 것이 더욱 중요시 되고 있다. 이러한 흐름에 맞추어 반도체 test장비에 VFCS(voltage forcing current sensing)와 CFVS(current forcing voltage sensing)를 test 할 수 있게 개발하였다.

• Journal of the Korean Society for Nondestructive Testing
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• v.21 no.6
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• pp.598-606
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• 2001

Recently, semiconductor packages trend to be thinner, which makes difficult to detect defects therein. A preconditioning test is generally performed to evaluate the reliability of semiconductor packages. The test procedure includes two scanning acoustic microscope (SAM) tests at the beginning and end of the entire test, in order to help detect physical defects such as delaminations and package cracks. In particular, of primary concern are package cracks and delaminations caused by moisture absorbed under ambient conditions. This paper discusses the failure mechanism associated with the moisture absorbed and encapsulated in semiconductors, and the use SAM to detect failures such as tracks and delaminations grown during the preconditioning test.

• Journal of IKEEE
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• v.25 no.3
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• pp.578-583
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• 2021

This paper describes acceleration tests for reliability of semiconductors. It also describes AEC-Q100, international test standard for reliability of automotive semiconductors. Semiconductors can be used for dozens of years. So acceleration tests are essential to test potential problems over whole period of product where test time is minimized by applying intensive stresses. AEC-Q100 is a typical acceleration test in automotive semiconductors, and it is designed to find various failures in semiconductors and to analyze their causes of occurance. So it finds many problems in design and fabrication as well as it predicts lifetime and reliability of semiconductors. AEC-Q100 consists of 7 test groups such as accelerated environmental stress tests, accelerated lifetime simulation tests, package assembly integrity tests, die fabrication reliability tests, electrical verification tests, defect screening tests, and cavity package integrity tests. It has 4 grades from grade 0 to grade 3 based on operational temperature. AEC-Q101, Q102, Q103, Q104, and Q200 are applied to discrete semiconductors, optoelectronic semiconductors, sensors, multichip modules, and passive components, respectively.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.22 no.1
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• pp.327-332
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• 2021

At the package level, semiconductor reliability inspections involves mounting a semiconductor chip package on a test socket. The form of the test socket is basically determined by the form of the chip package. It also acts as a medium to connect with test equipment through mechanical contact of the leads and socket leads in the chip package, and it minimizes signal loss in a signal transmission process so that an inspection signal can be delivered well to the semiconductor. In this study, a technique was applied to examine the interdependence of adjacent electrical transfer routes and the structure of adjacent electrical transfer paths. The goal was to enable short-circuit testing of fewer than 100 silicon test sockets through a single interface for life tests and precision measurements. The test results of the developed device show a test precision of 99% or more and a simultaneous test speed characteristic of 0.66 sec or less.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.6
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• pp.2472-2478
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• 2012

This research is aiming to develop Semiconductor equipment maintenance certification course to train qualified maintenance experts more effectively requested in related semiconductor industry. In the course of research, we adopted diverse research technique such as interview, on-spot investigation, documentary references to analyze current status of related training facilities, and forecast the population of test applicants. We analyzed similar certification course(Craftsman SMT, Industrial Engineer SMT, Craftsman Mechatronics, Industrial Enginee Mechatronics, et) as reference to set up job objectives and curriculum of semiconductor equipment maintenance certification. We conducted survey on expectations on newly created certificate, presented evaluation standard and objective of test, and preliminary writing test and demonstration test. Based on the result of various research, we were able to present training program for semiconductor equipment maintenance certification and set the assessment standard of qualification exam.

• Proceedings of the Korean Society of Computer Information Conference
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• 2018.07a
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• pp.357-359
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• 2018

최근 메모리 반도체 시장은 SD(Secure Digital) 메모리 카드, SSD(Solid State Drive)등의 보급률 증가로 메모리 반도체의 시장이 대규모로 증가하고 있다. 메모리 반도체는 개인용 컴퓨터 뿐만 아니라 스마프폰, 테플릿 PC, 교육용 임베디드 보드 등 다양한 산업에서 이용 되고 있다. 또한 메모리 반도체 생산 업체가 대규모로 메모리 반도체 산업에 투자하면서 메모리 반도체 시장은 대규모로 성장되었다. 플래시 메모리는 크게 NAND-Type과 NOR-Type으로 나뉘며 플로팅 게이트 셀의 전압의 따라 SLC(Single Level Cell)과 MLC(Multi Level Cell) 그리고 TLC(Triple Level Cell)로 구분 된다. SLC 및 MLC NAND-Type 플래시 메모리는 많은 연구가 진행되고 이용되고 있지만, TLC NAND-Tpye 플래시 메모리는 많은 연구가 진행되고 있지 않다. 본 논문에서는 기존에 제안된 SLC 및 MLC NAND-Type 플래시 메모리에서 제안된 큐브 패턴을 TLC NAND-Type 플래시 메모리에서 적용 가능한 큐브 패턴 및 알고리즘을 제안한다.

• Journal of the Semiconductor & Display Technology
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• v.22 no.1
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• pp.49-53
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• 2023

In this paper, we propose an antirandom pattern-based test method considering power consumption to compensate for the problem that the fault coverage through random test decreases or the test time increases significantly when the DUT circuit structure is complex or large. In the proposed method, a group unit test pattern generation process and rearrangement process are added to improve the problems of long calculation time and high-power consumption, which are disadvantages of the previous antirandom test.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.05a
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• pp.843-844
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• 2012

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.507-511
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• 2018

This paper proposes a method for system development for high speed (300MHz) test of system IC semiconductors. The high-speed test system proposes a high-speed test circuit interface and a PCB design method for noise reduction. This paper proposes evaluation items and procedures for verifying the performance of the developed system. System IC The development of high speed test systems will help optimize the development of domestic system IC test equipment.

• Journal of the Semiconductor & Display Technology
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• v.20 no.3
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• pp.146-151
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• 2021

We introduce an arbitrary waveform generation method and its H/W implementation case based on Rademacher and Walsh function. According to the orthogonal and periodic features of Rademacher and Walsh function, simple calculations can generate arbitrary waves with affordable logics. We implemented an FPGA-based AWS using above two functions, and verified. HDL simulation shows the proposed idea can draw desired analog test waveforms very fast, and its H/W size is promising to Built-Out Self-Test(BOST) logics for AI ICs.