• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.4
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• pp.323-330
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• 2002

In this paper, we have designed and fabricated an BWLL MMIC amplifier using GaAs PHEMT devices. We have optimized power divider/combiner size for small size of MMIC amplifier Using 0.2 ${\mu}$m AIGaAs/lnGaAs/GaAs PHEMT devices, the two stave MMIC amplifier has demonstrated a S$_{21}$ gain of 8.7 ㏈ with input/output return losses of lower than -10 ㏈ at 26.7 GHz. The size of this chip is 4.11 ${\times}$ 2.66 $\textrm{mm}^2$.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.05a
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• pp.503-507
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• 2002

Mask manufacturing is a high COC and COO process in developing of semiconductor devices, because of the mass production tool with high resolution. Direct writing has been thought to be one of the patterning method to cope with development or small-lot production of the device. This study focused on the development of the direct, mastless patterning process using stereolithography tool for the easy and convenient application to micro and miso scale products. Experiments are utilized by three dimensional CAD/CAM as a mask and photo-curable resin as a photo-resist in a conventional stereo-lithography apparatus. Results show that the resolution of the pattern was achieved about 300 micron because of complexity of SLA apparatus settings, inspite of 100 micro of inherent resolution. This paper concludes that photo resist and laser spot diameter should be adjusted to get finer patterns and the proposed method is significantly feasible to mastless and low cost patterning with micro and miso scale.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.101-107
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• 1994

The PMMA/Ge/AZ trilayer resist decreased proximity effect of backscattering electrons and corrected pattern distoration in order to from deep submicron patterns. In the experiment, the prosiemity effect is decreased by 11% and 30% for the case of 0.9$\mu$m and 1.7$\mu$m AZ, respectively, in trilayer resist compared to monolyer resist. also, the EID of 240$\AA$ Ge film is smaller than that of 500$\AA$ film by 365. 0.1$\mu$m line/space was formed in the 2000$\AA$ PMMA layer with the condition of dose 330${\mu}C/cm^{2}$ and of 150sec of develop time in MIBK : IPA (1:3) developer.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.1
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• pp.200-205
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• 1995

The 1st and 2nd-order grating structure for long wavelength DFB(Distributed FeedBack) laser diodes are successfully fabricated on InP substrates by using electron beam lithography and reactive ion etch techniques, and also characterized non-destructively by diffraction analysis without removal of photo-resis layer. A new composite layer made by lifted-off Cr layer on thin SiO2 film is developed and used as an etch mask, because PMMA, the e-beamresist, is unsuitable for reactive ion etch of InP. In addition, it is experimentally confiremed that diffraction analysis makes it possible to predict the grating parameters, and the analysis can be used as a non-destructive on-line test to prevent incomplete gratings from being successively processed.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.189-192
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• 2001

We have studied fabrication processes that form asymmetric $\Gamma$-gate with a 0.1${\mu}{\textrm}{m}$ gate length in MMIC's(Monolithic Microwave Integrated Circuits). Asymmetric $\Gamma$-gate was fabricated using mixture of PMMA and MCB. Thus pseudomorphic high electron mobility transistor (PHEMT's) with 0.1${\mu}{\textrm}{m}$ gate length was fabricated via several steps such as mesa isolation, metalization, recess, passivation. PHEMT's has the -1.75 V of pinch-off voltage (Vp), 63 mA of drain saturation current(Idss and 363.6 mS/mm of maximum transconductance (Gm) in DC characteristics and current gain cut-off frequency of 106 GHz and maximum frequency of oscillation of 160 GHz in RF characteristics.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.187-190
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• 1999

We have developed fabrication processes that form a wide-head T-gate with a 0.2 ${\mu}{\textrm}{m}$ gate length using the combination of thickness of each PMMA layer, line doses and development times for applications in millimeter- and micro-waves monolithic integrated circuits. The three-layer resist structure (PMMA/P(MMA-MAA)/PMMA = 1800 $\AA$/5800 A/1900$\AA$), 4nC/cm and over development were used for fabrication of a wide-head T-gate by the conventional double E-beam exposure technology. The experimented results show that the cross sectional area of T-gate fabricated by the proposed method is easily enlarged without additional processes.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2019.05a
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• pp.156-158
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• 2019

S-126 해양물리환경 국제표준에 대하여 S-101 전자해도 표준과 중첩하여 ECDIS(Electronic Chart Display and Information System) 상에 표현하는 방안에 대하여 연구하였다. 수로서지의 텍스트 기반 자료 형태인 해양물리현상을 기호화하여 전자해도에 중첩하여 표현함으로써 S-126 표준 정보를 ECDIS 사용자에게 보다 명확하게 전달하고, 그 결과 선박사고 및 안전항행에 기여할 것으로 기대된다.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.9
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• pp.42-47
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• 1998

We have fabricated electron-optical lens for micro E-beam system that can overcome the limitation of current E-beam lithography. Our electron-optical lens consists of multiple silicon electrodes which were fabricated by micromachining technology and assembled by anodic bonding. The assembled system was installed in UHV chamber to observe the emission characteristics of focused electrons by the electro-optical lens. We used STM(Scanning Tunneling Microscope) tip for electron source. By performing lithography with the focused electrons with PMMA(poly-methylmethacrylate) as E-beam resist. We could draw 0.13${\mu}{\textrm}{m}$ nano-scale lines.

• Korean Journal of Optics and Photonics
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• v.7 no.4
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• pp.333-340
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• 1996

We have implemented a planar integrated optics for the fractional Fourier transform (FRT) which has recently been developed as a generalized form of the conventional Fourier transform. FRT optical systems provide versatile tools for analyzing signals and designing hardwares, but require high accuracy and stability in the arrangement of optical components because of their shift-variant characteristic. The planar optical FRT setup composed of free-space optical components integrated on a single glass block makes the FRT of 2-dimensional(2-D) input patterns through the 3-D glass-space. Therefore, taking advantage of the compactness, easy alignment and thermal/mechanical stability, the planar optics can provide a useful approach to realizing an optical fractional correlation system in a practical way. In the experiment, we have obtained accurate FRT results by using the planar integrated optics with 4 different fractional orders of 0.25, 0.5, 0.75, and 1.0.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.48-52
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• 1998

We fabricated the newly proposed nano structure memory with SOI edge channel and a nano dot. The width of the edge channel of this device, which uses the side wall as a channel and has a nano dot on this channel region, was determined by the thickness of the recessed top-silicon layer of SOI wafer. The size of side-wall nano dot was determined by the RIE etch and E-Beam lithography. The I$_{d}$-V$_{d}$, I$_{d}$-V$_{g}$ characteristics of the devices without nano dots and memory characteristics of the devices with nano dots were obtained, where the voltage scan was done between -20 V and 14 V and the threshold voltage shift was about 1 V.t 1 V.