• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.11
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• pp.1707-1712
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• 2013

In this paper, we implement a hardware for motor control based on FPGA + embedded processor using Zynq EPP which is All Programmable SoC in order to improve a structural problem of motion control based on such as DSP, MCU and FPGA previously. The implemented motor controller that is fused controller with advantage of FPGA and embedded processor. The signal processing part of high velocity motor control is performed by motor controller based on FPGA. A motion profile and kinematic calculation that are required algorithm process such as operation of a complicate decimal point has processed in an embedded processor based on dual core. As a result of a hardware implementation, it has an advantage that has can be realized an effect of distribution process in one chip. It has also an advantage that is able to organize as a multi-axis motor controller through adding the IP core of motor control implemented on FPGA.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.888-889
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• 2015

This paper presents a method of constructing the system-on-chip(SoC) based on embedded systems. The proposed method is more compact and effectiveness than former methods. The requirements generation start high level performance simulation and then passes to an executable specification suitable for implementation using a hardware/software co-design tool. The reuse of pre-exiting components is supported, as well as synthesis of the system interface, but only after much work is done to program the hardware/software co-design tool. The actual design flow described allows feedback among all design levels, e.g. from implementation up to requirements, throughout the process. In the future, it is necessary to development the advanced method of constructing system-on-chip based on embedded systems.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.481-484
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• 2007

This paper presents a method of constructing the system-on-chip(SoC) based on embedded systems. The proposed method is more compact and effectiveness than former methods. The requirements generation start high level performance simulation and then passes to an executable specification suitable for implementation using a hardware/software co-design tool. The reuse of pre-exiting components is supported, as well as synthesis of the system interface, but only after much work is done to program the hardware/software co-design tool. The actual design flow described allows feedback among all design levels, e.g. from implementation up to requirements, throughout the process. In the future, it is necessary to development the advanced method of constructing system-on-chip based on embedded systems.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.5
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• pp.468-476
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• 2000

Binding the object-oriented programming language C++ with a database management system provides a persistency to C++ programming objects so that objects can persist after program termina~,on. In such a binding system, we can manage a persistent object same as that we use a transient object and also use database management facilities such as transaction management and concurrency control. This paper presents a method providing the persistency to C++ programming objects in the binding system. We propose an improved interface based on C++ binding of ODMG-97 and present the design and implementation technique of it. The proposed interface provides a seamless interface for creating objects of the persistent capable class. We can create a persistent object without its class name as we do not give a class name when creating a transient object. Also, we guarantee the type compatibilty between the obiect created in database and the obiect created in main memory.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.3
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• pp.355-366
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• 2022

This paper proposes a microcode-based neural network accelerator controller for artificial intelligence accelerators that can be reconstructed using a programmable architecture and provide the advantages of low-power and ultra-small chip size. In order for the target accelerator to support various neural network models, the neural network model can be converted into microcode through microcode compiler and mounted on accelerator to control the operators of the accelerator such as datapath and memory access. While the proposed controller and accelerator can run various CNN models, in this paper, we tested them using the YOLOv2-Tiny CNN model. Using a system clock of 200 MHz, the Controller and accelerator achieved an inference time of 137.9 ms/image for VOC 2012 dataset to detect object, 99.5ms/image for mask detection dataset to detect wearing mask. When implementing an accelerator equipped with the proposed controller as a silicon chip, the gate count is 618,388, which corresponds to 65.5% reduction in chip area compared with an accelerator employing a CPU-based controller (RISC-V).

• Proceedings of the Korean Society for Rock Mechanics Conference
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• 2000.09a
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• pp.93-103
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• 2000

The concrete plug in an underground cavern prevents the stored product (oil, gas, etc) from leaking and the excessive show of underground water, so it plays an important role in construction and operation of the storage cavern. Additionally, it should maintain its stability under every possible loading condition. Once the plug is constructed, the cavern is isolated from the external access. Therefore, mechanical and hydraulic consideration should be made in construction to fulfill its function. Therefore, in this study, numerical analyses were conducted to study the optimal shape and thickness of the plug with respect to the various conditions of installation depth, the shape of the plug, in-situ stress ratio (K), the condition of rock-plug interface, and the effect of Excavation Damaged Zone (EDZ). This paper also presents the effect of slot depth on the hydraulic behavior of the plug. These analyses were carried out by using the 2-dimensional finite difference code, rm FLAC, and the 3D code, m FLA $C^{3D}$./.

• Journal of the HCI Society of Korea
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• v.1 no.1
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• pp.37-44
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• 2006

Specular reflections provide the visual feedback that describes the material type of an object, its local shape, and lighting environment. In photorealistic rendering, there have been a number of research available to render specular reflections effectively based on a local reflection model. In traditional cel animations and cartoons, specular reflections plays important role in representing artistic intentions for an object and its related environment reflections, so the shapes of highlights are quite stylistic. In this paper, we present a method to render and control stylized specular reflections using projective textures based on principal curvature analysis. Specifying a texture as a pattern of a highlight and projecting the texture on the specular region of a given 3D model, we can obtain a stylized representation of specular reflections. For a given polygonal model, a view point, and a light source, we first find the maximum specular intensity point, and then locate the texture projector along the line parallel to the normal vector and passing through the point. The orientation of the projector is determined by the principal directions at the point. Finally, the size of the projection frustum is determined by the principal curvatures corresponding to the principal directions. The proposed method can control the position, orientation, and size of the specular reflection efficiently by translating the projector along the principal directions, rotating the projector about the normal vector, and scaling the principal curvatures, respectively. The method is be applicable to real-time applications such as cartoon style 3D games. We implement the method by Microsoft DirectX 9.0c SDK and programmable vertex/pixel shaders on Nvidia GeForce FX 7800 graphics subsystems. According to our experimental results, we can render and control the stylized specular reflections for a 3D model of several ten thousands of triangles in real-time.

• Journal of Life Science
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• v.20 no.3
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• pp.411-415
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• 2010

Anisakis simplex is one of the parasitic nematodes, and has a complex life cycle in crustaceans, fish, squid or whale. When people eat under-processed or raw fish, it causes anisakidosis and also plays a critical role in inducing serious allergic reactions in humans. However, no web-based database on A. simplex at the level of DNA or protein has been so far reported. In this context, we constructed a web-based database for Anisakis research. To build up the web-based database for Anisakis research, we proceeded with the following measures: First, sequences of order Ascaridida were downloaded and translated into the multifasta format which was stored as database for stand-alone BLAST. Second, all of the nucleotide and EST sequences were clustered and assembled. And EST sequences were translated into amino acid sequences for Nuclear Localization Signal prediction. In addition, we added the vector, E. coli, and repeat sequences into the database to confirm a potential contamination. The web-based database gave us several advantages. Only data that agrees with the nucleotide sequences directly related with the order Ascaridida can be found and retrieved when searching BLAST. It is also very convenient to confirm contamination when making the cDNA or genomic library from Anisakis. Furthermore, BLAST results on the Anisakis sequence information can be quickly accessed. Taken together, the Web-based database on A. simplex will be valuable in developing species specific PCR markers and in studying SNP in A. simplex-related researches in the future.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.8C
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• pp.575-582
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• 2008

In this paper we described the process and the results of real-time implementation of G.729.1 wideband speech codec which is standardized in SG15 of ITU-T. To apply the codec on ARM926EJ-S(R) processor core. we transformed some parts of the codec C program including basic operations and arithmetic functions into assembly language to operate the codec in real-time. G.729.1 is the standard wideband speech codec of ITU-T having variable bit rates of $8{\sim}32kbps$ and inputs quantized 16 bits PCM signal per sample at the rate of 8kHz or 16kHz sampling. This codec is interoperable with the G.729 and G.729A and the bandwidth extended wideband($50{\sim}7,000Hz$) version of existing narrowband($300{\sim}3,400Hz$) codec to enhance voice quality. The implemented G.729.1 wideband speech codec has the complexity of 31.2 MCPS for encoder and 22.8 MCPS for decoder and the execution time of the codec takes 11.5ms total on the target with 6.75ms and 4.76ms respectively. Also this codec was tested bit by bit exactly against all set of test vectors provided by ITU-T and passed all the test vectors. Besides the codec operated well on the Internet phone in real-time.

• Proceedings of the Korean Radioactive Waste Society Conference
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• 2005.06a
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• pp.311-318
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• 2005

Transparency on the Total System Performance Assessment (TSPA) is the key issue to enhance the public acceptance for a permanent high level radioactive repository. To approve it, all performances on TSPA through Quality Assurance is necessary. The integrated Cyber R&D Platform is developed by KAERI using the T2R3 principles applicable for five major steps in R&D's. The proposed system is implemented in the web-based system so that all participants in TSPA are able to access the system. It is composed of FEAS (FEp to Assessment through Scenario development) showing systematic approach from the FEPs to Assessment methods flow chart, PAID (Performance Assessment Input Databases) showing PA(Performance Assessment) input data set in web based system and QA system receding those data. All information is integrated into Cyber R&D Platform so that every data in the system can be checked whenever necessary. For more user-friendly system, system upgrade included input data & documentation package is under development. Throughout the next phase R&D, Cyber R&D Platform will be connected with the assessment tool for TSPA so that it will be expected to search the whole information in one unified system.