• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.420-435
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• 2001

As multimedia technology has rapidly grown recently, many researches to process multimedia data efficiently using general-purpose processors have been studied. In this paper, we proposed multimedia instructions which can process multimedia data effectively, and suggested a processor architecture for those instructions. The processor was described with Verilog-HDL in the behavioral level and simulated with CADENCE$^{TM}$ tool. Proposed multimedia instructions are total 48 instructions which can be classified into 7 groups. Multimedia data have 64-bit format and are processed as parallel subwords of 8-bit 8 bytes, 16-bit 4 half words or 32-bit 2 words. Modeled processor is developed based on the Integer Unit of SPARC V.9. It has five-stage pipeline RISC architecture with Harvard principle.e.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.5
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• pp.153-164
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• 2010

A program consumes energy by executing its instructions. The amount of cosumed power is mainly proportional to algorithm complexity and it can be calculated by using complexity information. Generally, the complexity of a S/W is estimated by the microprocessor simulator. But, the simulation takes long time why the simulator is a software modeled the hardware and it only provides the information about computational complexity quantitatively. In this paper, we propose a complexity estimation method of analysis of S/W on source code level and produce the complexity metric mathematically. The function-wise complexity metrics give the detailed information about the calculation-concentrated location in function. The performance of the proposed method is compared with the result of the gate-level microprocessor simulator 'SimpleScalar'. The used softwares for performance test are $4{\times}4$ integer transform, intra-prediction and motion estimation in the latest video codec, H.264/AVC. The number of executed instructions are used to estimate quantitatively and it appears about 11.6%, 9.6% and 3.5% of error respectively in contradistinction to the result of SimpleScalar.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10c
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• pp.385-387
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• 2002

이 논문에서 우리는 각 기능 블록의 성능 분석 방법을 제안하고 어떻게 하드웨어와 소프트웨어의 합성을 위한 기능 블록의 성능을 기록한 데이터베이스를 구축하는지를 설명하겠다. 기능 블록의 성능을 예측하는 것은 초기 설계 단계에서 주어진 제약을 만족시키기 위해 어떤 기능 블록이 개선되어야 할지 결정하는 기준을 제시하기 때문에 내장형 시스템의 합성에 있어서 중요하다. 예측하는 도구로 측정에 시간이 많이 걸리지만 정확한 명령어 수준 시뮬레이터(ISS : instruction set simulator)를 사용하였다. 데이터베이스를 구축하는데 있어선 각 기능 블록을 요소(factor)라 부르는 다른 상태를 두어서 차별화 하였다. 제안한 예측 방법은 개발중인 통합설계 환경에 구현되었으며 H.263 인코더에 적용하여 0.03% 이내의 오차를 얻었다.

• Proceedings of the Korean Information Science Society Conference
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• 2005.11a
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• pp.769-771
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• 2005

유비쿼터스 컴퓨팅의 기반 설비인 센서 네트워크는 많은 수의 센서 노드들로 구성되며, 각 센서 노드의 하드웨어는 매우 작은 규모이다. 또한 최소한의 전력 소모를 위하여 센서 노드들은 동적으로 재구성되며, 노드들 간의 통신은 무선 네트워크를 통하여 이루어진다. 센서 네트워크는 구축 목적에 따라 네트워크 토폴로지 및 라우팅 방식이 결정되어야 하고, 이와 더불어 센서 노드의 하드웨어와 소프트웨어도 필요에 따라 다양하게 변경되어야 한다. 따라서 센서 네트워즈가 구현되기 전에 시스템 동작과 성능을 예측할 수 있고 소프트웨어 개발 환경도 제공해주는 시뮬레이터가 사용 가능하다면, 시스템 개발 기간을 크게 단축시킬 수 있을 것이다. 기존의 센서 네트워크 시뮬레이터들은 특별한 응용을 위한 특정 기반의 하드웨어와 운영체제에 국한되어 개발되었기 때문에 다양한 센서 네트워크 환경을 지원하기에는 한계가 있으며, 센서 네트워크 설계상의 주요 요소인 전력 소모량 분석이 포함되지 않았다. 따라서 본 연구에서는 특정한 응용이나 운영체제에 제한을 받지 않으면서 다양하게 센서 네트워크 환경을 설계 및 검증할 수 있고 전력 소모량 추정도 가능한 시뮬레이터를 개발하는 것을 목표로 하였다. 본 연구에서 개발한 시뮬레이터는 기계명령어-레일(machine instruction-level)의 이산-사건 시뮬레이션(discrete-event simulation) 기법을 이용함으로써 실제 센서 노드의 프로그램 실행 및 관련 동작들을 세부적으로 예측하는 데 사용될 수 있도록 하였다. 시뮬레이션의 작업부하(Workload)인 명령어 트레이스(instruction trace)로는 ATmega128L 마이크로컨트롤러용으로 크로스 컴파일된 인텔 헥스-레코드 형식(.hex) 또는 S-레코드 형식(.srec)의 파일을 사용한다.들을 해결하고자 프라이버시보호에 새로운 키 생성 방법을 통한 강력한 프로토콜을 제안 한다.하였으나 사료효율은 증진시켰으며, 후자(사양, 사료)와의 상호작용은 나타나지 않았다. 이상의 결과는 거세비육돈에서 1) androgen과 estrogen은 공히 자발적인 사료섭취와 등지방 침적을 억제하고 IGF-I 분비를 증가시키며, 2) 성선스테로이드호르몬의 이 같은 성장에 미치는 효과의 일부는 IGF-I을 통해 매개될 수도 있을을 시사한다. 약 $70 {\~} 90\%$의 phenoxyethanol이 유상에 존재하였다. 또한, 미생물에 대한 항균력도 phenoxyethanol이 수상에 많이 존재할수록 증가하는 경향을 나타내었다. 따라서, 제형 내 oil tomposition을 변화시킴으로써 phenoxyethanol의 사용량을 줄일 수 있을 뿐만 아니라, 피부 투과를 감소시켜 보다 피부 자극이 적은 저자극 방부시스템 개발이 가능하리라 보여 진다. 첨가하여 제조한 curd yoghurt는 저장성과 관능적인 면에서 우수한 상품적 가치가 인정되는 새로운 기능성 신제품의 개발에 기여할 수 있을 것으로 사료되었다. 여자의 경우 0.8이상이 되어서 심혈관계 질환의 위험 범위에 속하는 수준이었다. 삼두근의 두겹 두께는 남녀 각각 $20.2\pm8.58cm,\;22.2\pm4.40mm$으로 남녀간에 유의한 차이는 없었다. 조사대상자의 식습관 상태는 전체 대상자의 $84.4\%$가 대부분이 하루 세끼 식사를 규칙적으로 하고 있었으며 식사속도는 허겁지겁 빨리 섭취하는 경우가 남자는 $31.0\%$, 여자는 $21.4\%$로 나타났고 이들을 제외한 나머지 사람들은 보통 속도 혹은 충분한 시간을 가지고 식사를 하였

• KIPS Transactions on Computer and Communication Systems
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• v.1 no.1
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• pp.1-10
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• 2012

The way-lookup cache and the way-tracking cache are considered to be the most energy-efficient when used for level 1 and level 2 caches, respectively. This paper proposes an energy-efficient set-associative cache using the bi-mode way-selector that combines the way selecting techniques of the way-tracking cache and the way-lookup cache. The simulation results using an Alpha 21264-based system show that the bi-mode way-selecting L1 instruction cache consumes 27.57% of the energy consumed by the conventional set-associative cache and that it is as energy-efficient as the way-lookup cache when used for L1 instruction cache. The bi-mode way-selecting L1 data cache consumes 28.42% of the energy consumed by the conventional set-associative cache, which means that it is more energy-efficient than the way-lookup cache by 15.54% when used for L1 data cache. The bi-mode way-selecting L2 cache consumes 15.41% of the energy consumed by the conventional set-associative cache, which means that it is more energy-efficient than the way-tracking cache by 16.16% when used for unified L2 cache. These results show that the proposed cache can provide the best level of energy-efficiency regardless of the cache level.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.5
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• pp.199-212
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• 2008

Software simulation has been widely used for the design and application development of a large-scale wireless sensor network. The degree of details of the simulation must be high to verify the behavior of the network and to estimate its execution time and power consumption of an application program as accurately as possible. But, as the degree of details becomes higher, the simulation time increases. Moreover, as the number of sensor nodes increases, the time tends to be extremely long. We propose an optimal-synchronous parallel discrete-event simulation method to shorten the time in a large-scale sensor network simulation. In this method, sensor nodes are partitioned into subsets, and each PC that is interconnected with others through a network is in charge of simulating one of the subsets. Results of experiments using the parallel simulator developed in this study show that, in the case of the large number of sensor nodes, the speedup tends to approach the square of the number of PCs participating in the simulation. In such a case, the ratio of the overhead due to parallel simulation to the total simulation time is so small that it can be ignored. Therefore, as long as PCs are available, the number of sensor nodes to be simulated is not limited. In addition, our parallel simulation environment can be constructed easily at the low cost because PCs interconnected through LAN are used without change.

• Journal of the Korea Society for Simulation
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• v.15 no.1
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• pp.35-42
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• 2006

Sensor network, that is an infrastructure of ubiquitous computing, consists of a number of sensor nodes of which hardware is very small. The network topology and routing scheme of the network should be determined according to its purpose, and its hardware and software may have to be changed as needed from time to time. Thus, the sensor network simulator being capable of verifying its behavior and estimating performance is required for better design. Sensor network simulators currently existing have been developed for specific hardwares or operating systems, so that they can only be used for such systems and do not provide any means to estimate the amount of power consumption and program execution time which are major issues for system design. In this study, we develop the sensor network simulator that can be used to design and verify various sensor networks without regarding to types of applications or operating systems, and also has the capability of predicting the amount of power consumption and program execution time. For this purpose, the simulator is developed by using machine instruction-level discrete-event simulation scheme. As a result, the simulator can be used to analyze program execution timings and related system behaviors in the actual sensor nodes in detail. Instruction traces used as workload for simulations are executable images produced by the cross-compiler for ATmega128L microcontroller.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.37-47
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• 2011

Real picture like high quality computer graphic is widely used in various fields and shader processor, a key part of a graphic processor, has been advanced to programmable unified shader. However, The existing graphic processors have been optimized to commercial algorithms, so development of an algorithm which is not based on it requires an independent shader processor. In this paper, we have designed and implemented a control unit to support high quality 3 dimensional computer graphic image on programmable integrated shader processor. We have done evaluation through functional level simulation of designed control unit. Hardware resource usage rate are measured by implementing directly on FPGA Virtex-4 and execution speed are verified by applying ASIC library. the result of an evaluation shows that the control unit has the commands more about 1.5 times compared to the other shader processors that is a behavior similar to the control unit and with a number of processing units used in a shader processor, compared with the other processors, overall performance of the control unit is improved about 3.1 GFLOPS.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.102-110
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• 2004

In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.