• The Journal of the Korea Contents Association
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• v.10 no.6
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• pp.72-79
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• 2010

In this paper, we propose the data cache architecture with a write buffer for a 32bit asynchronous embedded processor. The data cache consists of CAM and data memory. It accelerates data up lood cycle between the processor and the main memory that improves processor performance. The proposed data cache has 8 KB cache memory. The cache uses the 4-way set associative mapping with line size of 4 words (16 bytes) and pseudo LRU replacement algorithm for data replacement in the memory. Dirty register and write buffer is used for write policy of the cache. The designed data cache is synthesized to a gate level design using $0.13-{\mu}m$ process. Its average hit rate is 94%. And the system performance has been improved by 46.53%. The proposed data cache with write buffer is very suitable for a 32-bit asynchronous processor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.8
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• pp.1169-1174
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• 2002

In this paper, we implemented the sign board system that displays user's image, user's sentence, the information from DARC. The existing sign board is displaying only user's image and sentence. Or other existing sign board is displaying the information via CDMA network. However, our system is also able to display the user's message like other system and gain the information more cheap by DARC. This system includes the main processor, the program memory, the external memory, the DARC module and the LED display module. The external memory stores the user's message files and the order file that decides the displaying order of user's file and the DARC information The DARC module extracts the DARC information from FM signal. From the experiment, we could confirm that this system display the DARC information and the user's message by the order file.

• Journal of KIISE:Databases
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• v.29 no.5
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• pp.347-357
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• 2002

Graphs have provided a powerful methodology to solve a lot of real-world problems, and therefore there have been many proposals on the graph representations and algorithms. But, because most of them considered only memory-based graphs, there are still difficulties to apply them to large-scale problems. To cope with the difficulties, this paper proposes a graph representation and graph algorithms based on the well-developed relational database theory. Graphs are represented in the form of relations which can be visualized as relational tables. Each vertex and edge of a graph is represented as a tuple in the tables. Graph algorithms are also defined in terms of relational algebraic operations such as projection, selection, and join. They can be implemented with the database language such as SQL. We also developed a library of basic graph operations for the management of graphs and the development of graph applications. This database approach provides an efficient methodology to deal with very large- scale graphs, and the graph library supports the development of graph applications. Furthermore, it has many advantages such as the concurrent graph sharing among users by virtue of the capability of database.

• Journal of KIISE
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• v.42 no.4
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• pp.434-441
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• 2015

Next generation memory technologies, which we denote as 'new memory', have both non-volatile and byte addressable properties. These characteristics are expected to bring changes to the conventional computer system structure. In this paper, we propose a fast boot technique for hybrid main memory architectures that have both new memory and DRAM. The key technique used for fast booting is write-tracking. Write-tracking is used to detect and manage modified data detection and involves setting the kernel region to read-only. This setting is used to trigger intentional faults upon modification requests. As the fault handler can detect the faulting address, write-tracking makes use of the address to manage the modified data. In particular, in our case, we make use of the MMU (Memory Management Unit) translation table. When a write occurs to the boot completed state, write-tracking preserves the original state of the modified address of the kernel region to a particular location, and execution continues. Upon booting, the fast booting process restores the preserved data to the original kernel region allowing rapid system boot-up. We develop the fast booting technique in an actual embedded board equipped with new memory. The boot time is reduced to less than half a second compared to around 15 seconds that is required for the original system.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.49 no.2
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• pp.149-156
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• 2012

Support vector machines (SVMs) are well known for their pattern recognition capability, but proper care should be taken to alleviate their inherent implementation cost resulting from high computational intensity and memory requirement, especially in embedded systems where only limited resources are available. Since the memory requirement determined by the dimensionality and the number of support vectors is generally too high for a cache in embedded systems to accomodate, frequent accesses to the main memory occur inevitably whenever the cache is not able to provide requested data to the processor. These frequent accesses to the main memory result in overall performance degradation and increased energy consumption because a memory access typically takes longer and consumes more energy than a cache access or a register access. In this paper, we propose a technique that reduces the number of main memory accesses by optimizing the data access pattern of the SVM-based classifier in such a way that the temporal locality of the accesses increases, fully utilizing data loaded into the processor chip. With experiments, we confirm the enhancement made by the proposed technique in terms of the number of memory accesses, overall execution time, and energy consumption.

• Journal of Internet Computing and Services
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• v.6 no.1
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• pp.73-84
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• 2005

ALTIBASE/sup TM/ is the relational main-memory DBMS in which a main memory is primarily used as the main storage device. We present the database replication strategies and techniques of the ALTIBASETM system in order to meet the requirement of high availability and efficient transaction processing. Our process architecture for replication management and its communication model are proposed, and database replication protocols are also described. We show the experimental result of transaction processing rate with various DBMS parameters and overall performance of database replication system as compared to standalone system.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.2
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• pp.327-334
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• 2016

Contrary to the common belief, DRAM which is used for the main memory of various computing devices retains its content even though it is powered-off. Especially, the data-retaining time can increase if DRAM is cooled down. The Cold Boot Attack, a kind of side-channel attacks, tries to recover the sensitive information such as the cryptographic key from the powered-off DRAM. This paper proposes a new algorithm which recovers the AES key under the symmetric-decay cold-boot-attack model. In particular, the proposed algorithm uses the strategy of reducing the size of the candidate key space by testing the randomness of the extracted AES key bit stream.

• The Journal of the Korea Contents Association
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• v.5 no.3
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• pp.1-8
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• 2005

ALTIBASE is the relational main memory DBMS that enables us to develop the high performance and fault tolerant applications. It guarantees the short and predictable execution time as well as the basic functionality of conventional disk-based DBMS. We present the 'overview of system architecture and the performance analysis with respect to the various design choices. The assorted experiments are performed under the various environments. The results of TPC-H and Wisconsin benchmark tests are described. We illustrate the performance comparisons under the various index mechanisms, the replication models, and the transaction durabilities. A performance study shows the ALTIBASE system can be applied to the wide area of industrial DBMS fields.

• Journal of the Korean Institute of Intelligent Systems
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• v.16 no.1
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• pp.94-100
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• 2006

Computing paradigm shift to internet-based one has accelerated the use of XML in diverse applications. This phenomena has made the explosive increases of XML data and it triggered many active researches in maintaining very huge amount of XML data in turn. In this paper we present a persistent graph-based XML indexing lot data-centric XML data. In our approach we use 3 graphs to represent XML indexes and XML data itself. They are schema graph, data graph index. And then we have mapped those graphs to B+-trees the persistency. With our approach we can achieve linear query execution time with the increase of XML sizes.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.2
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• pp.179-185
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• 2020

DRAM is a major component of the main memory system. As the operating system evolves and application complexity and capacity increases, the capacity and speed of DRAM are also increasing. DRAM should perform a refresh action of periodically reading and then re-storing stored values, and the accompanying performance and power/energy overhead embodies characteristics that worsen as capacity increases. This study proposes an energy efficiency improvement technique that efficiently stores the rows that need to be refreshed within 64ms and 128ms using the bloom filter for cells with the lowest retention time of electrons. The results of the experiment showed that the proposed technique resulted in an average 5.5% performance improvement, 76.4% reduction in average refresh energy, and 10.3% reduction in average EDP.