• The Journal of Korean Institute of Next Generation Computing
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• v.13 no.4
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• pp.40-51
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• 2017

Recently, as mobile workloads are becoming more data-intensive, high data bandwidth is required for mobile memory which also consumes non-negligible system energy. A variety of researches and technologies are under development to improve and optimize mobile memory technologies. However, a comprehensive study on the latest mobile memory technologies (LPDDR or Wide I/O) has not been extensively performed yet. To construct high-performance and energy-efficient mobile memory systems, quantitative and detailed analysis of these technologies is crucial. In this paper, we simulate the computer system which adopts mobile DRAM technologies (Wide I/O and LPDDR3). Based on our detailed and comprehensive results, we analyze important factors that affect performance and energy-efficiency of mobile DRAM technologies and show which part can be improved to construct better systems.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.59-65
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• 2016

Performance optimization of applications with massive stream data processing has been performed by considering I/O data coherency problem where a memory is shared between processors and hardware accelerators. A formula for performance analyses is derived based on profiling results of system-level simulations. Our experimental results show that overall performance was improved by 1.40 times on average for various image sizes. Also, further optimization has been performed based on the parameters appeared in the derived formula. The final performance gain was 3.88 times comparing to the original design and we can find that the performance of the design with cacheable shared memory is not always.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.11
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• pp.836-840
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• 2009

Many researchers have studied flash memory in order to replace hard disk storages. Many FTL algorithms have been proposed to overcome physical constraints of flash memory such as erase-before-write, wear leveling, and poor write performance. Therefore, these constraints should be considered for testing FTL algorithms and the performance evaluation of flash memory. As doing the experiments, we suffer from several problems with costs and settings in experimental configuration. When we, for example, replay the traces of Oracle to evaluate the I/O performance with flash memory, it is hard to extract exact traces of I/O operations in Oracle. Since there are only write operations in the log, it is impossible to gather read operations. In MySQL and SQLite, we can gather the read operations by changing I/O functions in the source codes. But it is not easy to search for the exact points about I/O and even if we can find out the points, we might get wrong results depending on how we modify source codes to get I/O traces. The FlaSim proposed in this paper removes the difficulties when we evaluate the performance of FTL algorithms and flash memory. Our Linux drivers emulate the flash memory as a hard disk. And we can easily obtain the usage statistics of flash memory such as the number of write, read, and erase operations. The FlaSim can be gracefully extended to support the additional modules implemented by novel algorithms and ideas. In this paper, we describe the structure of FTL emulator, development tools and operating methods. We expect this emulator to be helpful for many experiments and research with flash memory.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.11a
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• pp.44-45
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• 2013

전 세계의 스마트폰 보급률이 증가와 함께 새로운 형태의 스마트 워치, 구글 글래스 등의 모바일 장비들이 등장하고 있다. 이는 제한된 자원을 사용하는 스마트폰 환경에서 효율적으로 CPU, 메모리, 저장 장치들을 효과적으로 사용하기 위한 연구를 필요로 한다. 이에 본 논문에서는 안드로이드 환경에서 부족 메모리의 공간 확보를 위해 동일한 내용의 페이지 캐시를 찾고, 중복 제거하는 기법을 제안한다. 이는 부족한 메모리 공간 확보와 캐시를 지속하여 I/O 연산의 빈도를 줄여 스마트폰 성능 향상을 가져올 것으로 기대된다.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.82-82
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• 2010

유기 쌍안정성 소자는 비휘발성 기억 소자 중에서 구조가 간단하고 제작비용이 저렴하며 유연성을 가지기 때문에 많은 연구가 진행되고 있다. 현재 유기물/무기물 나노복합소재를 사용하여 소자 성능 향상이 기억소자의 성능 향상을 위하여 여러 가지 유기물/무기물 나노복합소재를 사용하여 제작한 유기 쌍안정성 소자가 유연성을 가진 비휘발성 기억소자로 대두되고 있다. 본 연구에서는 ZnO 나노입자를 포함한 PMMA 복합층을 사용하여 제작한 유기 쌍안정성 기억소자를 제작하여 메모리 특성을 조사하였다. 이와 더불어 활성층에 효과적인 전하주입을 위하여 전극과 PMMA/ZnO 층 사이에 $C_{60}$ 층을 삽입한 구조를 가진 메모리 소자의 성능 향상에 대하여 연구하였다. Indium tin oxide 가 증착된 유리 기판위에 $C_{60}$ 층을 스핀코팅 방법으로 적층하였다. 1 wt% ZnO 나노입자와 1 wt% PMMA를 혼합하여 스핀코팅 방법으로 $C_{60}$ 층 위에 박막을 형성하였다. 그리고, 전극으로 Al을 열증착으로 형성하였다. $C_{60}$ 층이 있는 유기 쌍안정성 기억 소자와 $C_{60}$ 층이 없는 두 가지의 소자에 대하여 전류-전압 (I-V) 특성을 측정하여 각각의 소자에서의 전류 히스테리시스 현상이 발생하는 원인을 규명하였다. I-V 특성 결과와 전자적 구조를 사용하여 유기 쌍안정성 소자에서의 쓰기, 지우기 및 읽기 동작에 대한 과정을 설명하였다. 두 소자의 I-V 특성을 비교하므로 $C_{60}$ 층을 사용하여 유기 쌍안정성 소자의 성능이 향상됨을 알 수 있었다. 또한 $C_{60}$ 층을 사용하여 제작된 유기 쌍안정성 소자의 성능이 향상된 원인을 규명하였다.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.5
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• pp.412-421
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• 2009

Due to the physical characteristics of NAND flash memory, overwrite operations are not permitted at the same location, and therefore erase operations are required prior to rewriting. These extra operations cause performance degradation of NAND flash memory file system. Since it also has an upper limit to the number of erase operations for a specific location, frequent erases should reduce the lifetime of NAND flash memory. These problems can be resolved by delaying write operations in order to improve I/O performance: however, it will lower the cache hit ratio. This paper proposes a policy of page management using double cache for NAND flash memory file system. Double cache consists of Real cache and Ghost cache to analyze page reference patterns. This policy attempts to delay write operations in Ghost cache to maintain the hit ratio in Real cache. It can also improve write performance by reducing the search time for dirty pages, since Ghost cache consists of Dirty and Clean list. We find that the hit ratio and I/O performance of our policy are improved by 20.57% and 20.59% in average, respectively, when comparing them with the existing policies. The number of write operations is also reduced by 30.75% in average, compared with of the existing policies.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.6
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• pp.451-462
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• 2009

Recently, there are many active studies to enhance low I/O performance of hard disk device. The studies on the hardware make good progress whereas those of the system software to enhance I/O performance may not support the hardware performance due to its poor progress. In this paper, we propose a new method of prefetching n-blocks into the flash memory. The proposed method consists of three steps: (1)analyzing the pattern of read requests in block units; (2)determining the number of blocks prefetched to flash memory; (3)replacing blocks according to block replacement policy. The proposed method can reduce the latency time of hard disk and optimize the power consumption of the computer system. Experimental results show that the proposed dynamic n-block method provides better average response time than that of the existing AMP(Adaptive multi stream prefetching) method by 9.05% and reduces the average power consumption than that of the existing AMP method by 11.11%.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.1
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• pp.71-76
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• 2022

Buffer cache bridges the performance gap between memory and storage, but its effectiveness is limited due to periodic flush, performed to prevent data loss in smartphones. This paper shows that selective flushing technique with small persistent memory can reduce the flushing overhead of smartphone buffer cache significantly. This is due to our I/O analysis of smartphone applications in that a certain hot data account for most of file writes, while a large proportion of file data incurs single-writes. The proposed selective flushing policy performs flushing to persistent memory for frequently updated data, and storage flushing is performed only for single-write data. This eliminates storage write traffic and also improves the space efficiency of persistent memory. Simulations with popular smartphone application I/O traces show that the proposed policy reduces write traffic to storage by 24.8% on average and up to 37.8%.

• Journal of IKEEE
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• v.24 no.4
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• pp.1172-1175
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• 2020

Automotive ECU integrates CPU core, IVN controller, memory interface, sensor interface, I/O interface, and so on. Current automotive ECUs are often developed with proprietary processor architectures. However, demends for standard processors such as ARM and RISC-V increase rapidly for saftware compatibility in autonomous vehicles and connected cars. In this paper, an automotive ECU is designed for parking assist system based on RISC-V with open instruction set architecture. It includes 32b RISC-V CPU core, IVN controllers such as CAN and LIN, memory interfaces such as ROM and SRAM, and I/O interfaces such as SPI, UART, and I2C. Fabricated in 65nm CMOS technology, its operating frequency, area, and gate count are 50MHz, 0.37㎟, and 55,310 gates, respectively.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.3
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• pp.710-716
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• 2008

This paper covers the performance evaluation of two flash memory-based file storages, NAND and NOR, which are the major flash types. To evaluate their performances, we set up separate file storages for the two types of flash memories on a PocketPC-based experimental platform. Using the platform, we measured and compared the I/O throughputs in terms of buffer size, amount of used space, and kernel-level write caching. According to the results from our experiments, the overall performance of the NAND-based storage is higher than that of NOR by up to 4.8 and 5.7 times in write and read throughputs, respectively. The experimental results show the relative strengths and weaknesses of the two schemes and provide insights which we believe assist in the design of flash memory-based file storages.