• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.723-726
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• 2008

H.264/AVC는 다양한 블록 사이즈에 따라 움직임 보상을 수행한다. 본 논문은 1/4정밀도 화소를 지원하는 효율적인 움직임 보상에 대해 연구하였다. 참조 프레임의 데이터로 사용하기 위한 메모리의 접근을 줄이고 2개의 6-tap 필터를 사용하는 움직임 보상을 제안한다. 소프트웨어 검증을 통한 최적화 된 알고리즘을 사용하여 하드웨어 설계 언어를 이용하여 기술하고 ModeSim 6.0a를 이용한 데이터 검증을 수행하였다.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.831-834
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• 2003

본 논문에서 기술하고 있는 디블로킹 필터는 ISO/1EC 14496-2 의 디블로킹 필터링 알고리즘[1][2]을 기반으로 한다. 한 개의 레지스터 뱅크를 이용한 효율적인 데이터 스케줄링을 통해 면적과 전력 측면에서 디블로킹 필터를 사용함으로써 생기는 오버헤드를 최소화 시켰으며, CIF 급 영상을 27MHz 동작주파수에서 실시간으로 처리할 수 있도록 설계 하였다. 0.25㎛ Standard Cell Library 로 합성한 결과 총 9800 게이트로 구성 되었으며, 외부 메모리의 도움 없이 동작 시키기 위해 4.4KByte의 버퍼가 사용되었다.

• Proceedings of the Korea Information Processing Society Conference
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• 2015.04a
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• pp.114-117
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• 2015

이 논문에서는 소수 추출 방법인 Sieve of Eratosthenes 알고리즘을 병렬화하되 실행시간과 에너지 소모 면에서 개선된 효과를 얻고자 한다. 멀티코어 프로세서의 공유 메모리를 효율적으로 활용하도록 하이브리드 병렬 프로그래밍 모델을 적용하고, 부하 균등화를 정교하게 조절하도록 파이프라인 작업 방식을 도입하였다. 실험결과 이전 방식보다 연산속도가 향상되었고, 에너지 사용량도 감소함을 확인하였다.

• The Transactions of the Korea Information Processing Society
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• v.4 no.9
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• pp.2247-2258
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• 1997

Quadtree, which is hierarchical data structure, is a very important data structure to represent binary images. Since a linear quadtree representation as is a way to store a quadtree is efficient to save space compared with other representations. It is, however, complicated and takes a large amount of time to build the linear quadtree. In this paper, we present O(1) time a linear quadtree building algorithm for a $n{\times}n$ binary image using three-dimensional $n{\times}n{\times}n$ processors on RMESH structure. Our algorithm, by use of O(1) time collapsing algorithm and reported O(1) time sorting algorithm, is simpler and easier to understand than resently presented algorithm on PARBUS structure.

• Journal of the Korea Society for Simulation
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• v.18 no.4
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• pp.59-66
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• 2009

This has been possible by integration techniques such as very large scale integration (VLSI) and wafer scale integration (WSI). Redundancy has been extensively used for manufacturing memory chips and to provide repair of these devices in the presence of faulty cells. If there are too many defects, the momory has to be rejected. But if there are a few defects, it will be more efficient and cost reducing for the company to use it by repairing. Therefore, laser-repair process is nedded for such a reason and redundancy analysis is needed to establish correct target of laser-repair process. The proposed CRA (Correlation Repair Algorithm) simulation, beyond the idea of the conventional redundancy analysis algorithm, aims at reducing the time spent in the process and strengthening cost competitiveness by performing redundancy analysis after simulating each case of defect.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.57-62
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• 2011

In this paper, an efficient architecture for MFVLD(Multi-Format Variable Length Decoder) which can process H.264, MPEG-2, MPEG-4, AVS, VC-1 bitstream is proposed. The proposed MF-VLD is designed to be adapted to the MPSOC (Multi-processor System on Chip) architecture, uses bit-plane algorithm for the processing of inverse quantized data to reduce the width of AHB bus. External SDRAM is used to minimize the internal memory size. In this architecture, the adding or removing each variable length decoder can be easily done by using multiplexor. The designed MF-VLD can be operated in 200MHz at 0.18um process. The gate size is 657K gate and internal memory size is 27Kbyte.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.8
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• pp.1196-1204
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• 2022

In this paper, we propose an optimization algorithm that maximizes the network lifetime in wireless ad-hoc networks using the broadcast transmission method. The optimization algorithm proposed in this paper applies tabu search algorithm, a metaheuristic method that improves the local search method using the memory structure. The proposed tabu search algorithm proposes efficient encoding and neighborhood search method to the network lifetime maximization problem. By applying the proposed method to design efficient broadcast routing, we maximize the lifetime of the entire network. The proposed tabu search algorithm was evaluated in terms of the energy consumption of all nodes in the broadcast transmission occurring in the network, the time of the first lost node, and the algorithm execution time. From the performance evaluation results under various conditions, it was confirmed that the proposed tabu search algorithm was superior to the previously proposed metaheuristic algorithm.

• The KIPS Transactions:PartA
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• v.14A no.3 s.107
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• pp.151-158
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• 2007

Quadtree, which is a hierarchical data structure, is a very important data structure to represent images. The linear quadtree representation as a way to store a quadtree is efficient to save space compared with other representations. Therefore, it has been widely studied to develop efficient algorithms to execute operations related with quadtrees. The computation of block location is one of important geometry operations in image processing, which extracts a component completely including a given block. In this paper, we present a constant time algorithm to compute the block location of images represented by quadtrees, using three-dimensional $n\times n\times n$ processors on RMESH(Reconfigurable MESH). This algorithm has constant-time complexity by using efficient basic operations to deal with the locational codes of quardtree on the hierarchical structure of $n\times n\times n$ RMESH.

• Journal of the Korea Society of Computer and Information
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• v.14 no.3
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• pp.139-147
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• 2009

The memory based reasoning just stores in the memory in the form of the training pattern of the representative pattern. And it classifies through the distance calculation with the test pattern. Because it uses the techniques which stores the training pattern whole in the memory or in which it replaces training patterns with the representative pattern. Due to this, the memory in which it is a lot for the other machine learning techniques is required. And as the moreover stored training pattern increases, the time required for a classification is very much required. In this paper, We propose the EAS(Evaluation And Selection) algorithm in order to minimize memory usage and to improve classification performance. After partitioning the training space, this evaluates each partitioned space as MDL and PM method. The partitioned space in which the evaluation result is most excellent makes into the representative pattern. Remainder partitioned spaces again partitions and repeat the evaluation. We verify the performance of Proposed algorithm using benchmark data sets from UCI Machine Learning Repository.

• Journal of KIISE:Databases
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• v.35 no.6
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• pp.533-543
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• 2008

With technological advances for storage volume size of a semiconductor memory, USB storage is made as products to support a high capacity storage. Hereby, consumers discard pint-sized USB storages which they already had, or do not use them efficiently. To integrate and unify these pint-sized USB storages as one big USB storage, we proposed Sigma Hub. It can be grouping multiple USB storages, which have each different volume size of memory storage, as logical unity Storage through USB Hub. The proposed Sigma Hub includes Sigma Controller as a core management module to unify the multiple USB storages in transaction level layer. Sigma controller can efficiently control transaction packet in Sigma Hub through a USB Storage-Integration algorithms which ensure an integrity for data read and write processes. Consequently, Sigma Hub enables the use of USB storage that is logical unity.