• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.417-424
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• 2019

This paper presents the design of a JPEG-LS codec for lossless image compression from AR/VR device. The proposed JPEG-LS(: LosSless) codec is mainly composed of a context modeling block, a context update block, a pixel prediction block, a prediction error coding block, a data packetizer block, and a memory block. All operations are organized in a fully pipelined architecture for real time image processing and the LOCO-I compression algorithm using improved 2D approach to compliant with the SBT coding. Compared with a similar study in JPEG-LS, the Block-RAM size of proposed STB-FLC architecture is reduced to 1/3 compact and the parallel design of the predication block could improved the processing speed.

• Proceedings of the Korean Information Science Society Conference
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• 2005.11a
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• pp.613-615
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• 2005

모바일 기기가 가지는 다양한 화면 사이즈 등을 고려한 정보 서비스를 제공하기 위해서는 비트맵 기반의 JPG나 GIF 보다는 벡터 기반의 SVG, Flash Lite와 같은 이미지 포맷이 더 적합하다. 대부분의 모바일 기기의 경우 작은 메모리, 협소한 네트워크 대역폭, 불안전한 네트워크 연결 등과 같은 제약성을 가지고 있기 때문에 모바일 기기와 서버 간의 정보나 데이터의 망과 전송 시간을 단축시키기 위한 다양한 연구들이 진행되고 있다. 이에 본 논문에서는 모바일 기기에서 정보를 표현하기 위하여 사용되는 SVG와 같은 XML 파일들을 효과적으로 전송하기 위한 방법을 제안한다.

• Journal of Korea Society of Digital Industry and Information Management
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• v.5 no.3
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• pp.59-67
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• 2009

This paper proposes a improved bitmap routing protocol, which finds the best energy efficient routing path by minimizing the network overheads and prolongs the overall network lifetime. Jung proposed a bitmap scheme for sensor networks. His scheme uses a bitmap table to represent the connection information between nodes. However, it has a problem that the table size is depends on the number of nodes in the sensor networks. The problem is very serious in the sensor node with a limited memory. Thereby, this paper proposes a improved bitmap routing protocol to solve the problem in Jung's scheme. Proposed protocol over the memory restricted sensor network could optimize the size of bitmap table by applying the deployed network property. Proposed protocol could be used in the diversity of sensor networks due to it has minimum memory overheads.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10a
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• pp.52-54
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• 2003

본 논문에서는 30게임에서 삼각형 내접원을 이용한 이동경로의 곡선화를 제안한다. 일반적으로 게임에서는 맵(map)을 형성하기 위해 그리드(grid) 방식을 채택한다. 그러나 그리드 방식은 지형을 형성할 때 격자를 이용하므로 자연스러운 맵을 형성하기 어려우며, 세밀한 묘사를 위해서는 많은 수의 격자를 이용하여야함으로 경로탐색 시 연산시간과 메모리에 부담을 준다. 이러한 문제점을 해결하기 위해서 웨이포인트(waypoint)를 이용하여 이동경로를 설정하기도 하지만. 이러한 방법은 게임디자이너가 웨이포인트를 미리 설정하여야한다는 단점이 뒤따른다. 근래에는 이러한 문제점 해결을 위해 네비게이션 메쉬(navigation mesh)를 이용하기도 한다. 네비게이션 메쉬를 이용하면 맵을 간소화할 수 있고 빠른 자동 경로탐색을 이룰 수 있다. 그러나 이러한 네비게이션 메쉬에서 A＊ 알고리즘을 적용하여도 이동경로는 꺾은선으로 나타나게 되어 현실감을 떨어뜨리는 원인으로 작용된다. 이러한 이동경로의 곡선화 문제점을 해결하기 위해 본 논문에서는 삼각형 내접원을 이용하여 이동경로의 곡선화를 이루었다.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.5_6
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• pp.213-222
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• 2003

Most existing algorithms adopt the forward mapping method that is based on vector representation. Problem of existing algorithms Is the exponential increase of memory usage with number of layers. This degrades the accuracy of the boundary pattern representation. Our method uses bitmap representation and does not require any additional post-processing for conversion of vector-form results to bitmap-form. A new and efficient algorithm is presented in this paper for the generation of hyperbolic patterns by means of backward mapping methods.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.11a
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• pp.538-541
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• 2007

최근 SoC 기술이 발달하면서, 내장형 시스템을 위한 프로세서 개발이 활발해졌다. 새로운 프로세서가 개발되면, 운영체제 및 소프트웨어 개발을 위해 컴파일러 및 디버거가 필요하다. 컴파일러는 소스코드를 타겟 프로세서에서 실행 가능한 목적파일로 변환하고, 디버거는 프로그램의 개발에서 오류를 찾기 위한 도구로 소프트웨어 개발에 매우 중요한 도구들이다. 본 논문에서는 KAIST에서 개발하는 32bit 프로세서인 Core-A를 위한 소프트웨어 디버거를 설계 및 구현한다. Core-A용 디버거는 공개 소스 디버거 시스템인 GDB를 참조모델로 했으며, 레지스터와 메모리 맵과 같은 프로세서 종속적인 부분을 확장하고 외부 인터페이스 모듈과 같은 프로세스 독립적인 모듈은 재사용함으로써 개발기간을 단축시켰다. 그리고 Core-A용 디버거의 검증을 위해 상용 디버거 시스템인 ARM용 AXD 디버거와 비교 실험을 진행하였다.

• Journal of the Korea Society of Computer and Information
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• v.18 no.4
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• pp.27-34
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• 2013

Mobile robot has the exploration function in order to perform its own task. Robot exploration can be used in many applications such as surveillance, rescue and resource detection. The workspace that robots performed in was complicated or quite wide, the multi search using the several mobile robots was mainly used. In this paper, we proposed a scheme that all areas are searched for by using one robot. The method to be proposed extract a area that can be explored in the workspace then the robot investigates the area and updates the map at the same time. The explored area is saved as a hybrid map that combines the nice attributes of the grid and topological maps. The robot can produce the safe navigation route without the obstacles by using hybrid map. The proposed hybrid map uses less memory than a grid map, but it can be used for complete coverage with the same efficiency of a topological map. Experimental results show that the proposed scheme can generate a map of an environment with only 6% of the memory that a grid map requires.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.5
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• pp.1139-1144
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• 2008

In this paper, we propose an automatic generation method of transaction level(TL) model from algorithmic model to verify system specification fast and effectively using virtual platform. The TL virtual platform including structural properties such as timing, synchronization and real-time is one of the effective verification frameworks. However, whenever change system specification or HW/SW mapping, we must rebuild virtual platform and additional design/verification time is required. And the manual description is very time-consuming and error-prone process. To solve these problems, we build TL library which consists of basic components of virtual platform such as CPU, memory, timer. We developed a set of design/verification tools in order to generate a virtual platform automatically. Our tools generate a virtual platform which consists of embedded real-time operating system (RTOS) and hardware components from an algorithmic modeling. And for communication between HW and SW, memory map and device drivers are generated. The effectiveness of our proposed framework has been successfully verified with a Joint Photographic Expert Group (JPEG) and H.264 algorithm. We claim that our approach enables us to generate an application specific virtual platform $100x{\tims}1000x$ faster than manual designs. Also, we can refine an initial platform incrementally to find a better HW/SW mapping. Furthermore, application software can be concurrently designed and optimized as well as RTOS by the generated virtual platform

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.12
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• pp.3029-3034
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• 2014

The paper describes the scleral diagnostic system implementation for human eyes by using the scleral color code and vessels sign pattern code generations. The system is based on the high performance DSP image signal processor, programmable gain control for preprocessing and RISC SD frames storage. RGB image signals are optimized by PGC, the edge image is detected form the gray image converted. The processing algorithms are executed by scleral color code generation and scleral vessels sign pattern code creation for discriminating and matching. The scleral symptomatic color code is generated by YCbCr values at memory map tolerated and the vessel sign pattern code is created by digitizing the 24 clock and 13 ring zones, overlay matching and tolerances. The experimental results for performance are that the system runs 40ms, and the color and pattern for diagnostic errors are around 20% and 24% on average. The system and technique enable a scleral diagnosis with subdividing the patterns and patient database.

• Journal of Satellite, Information and Communications
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• v.8 no.2
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• pp.88-93
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• 2013

The wideband chirp signal generator to enhance the resolution of synthetic aperture radar of obtaining the earth observation image is needed. This paper deals with designing, manufacturing and testing the wideband digital chirp signal generator having high resolution for LEO earth observation satellite. The wideband digital chirp signal generator is implemented with the memory-map based structure which is mostly applied in the satellite, and consists of the digital module to generate the digital chirp signal and the RF module to perform the quadrature modulation. The I/Q signals stored in the memory of the digital module are D/A converted and delivered to be quadrature modulated with the reference signal of 1275 MHz in the RF module. Furthermore, the test bench and GUI to validate the signal generator function are also developed. It is found that the requirement of 144 MHz bandwidth for the digital chirp signal generator is well met. Finally it is noteworthy that the distortion occurred in the chirp signal generator was compensated by the pre-distortion compensation.