• Journal of KIISE:Computing Practices and Letters
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• v.16 no.12
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• pp.1199-1203
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• 2010

Data transfer between host system and storage device is based on the data unit called sector, which can be varied depending on computer systems. If NAND flash memory is used as a storage device, the variant sector size can affect storage system performance since its operation is much related to sector size and page size. In this paper, we propose an efficient FTL mapping management scheme to support multiple sector size within one NAND flash memory based storage device, and analyze the performance effect and management overhead. According to the proposed scheme, the management overhead of proposed FTL management is lower than conventional scheme when various sector sizes are configured in computer systems, while performance is less degraded in comparison with single sector size support system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.12B
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• pp.1418-1425
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• 2009

This paper proposes a novel FTL (Flash Translation Layer) algorithm based on sector-level mapping to reduce the number of total erase operations in flash memory accesses. The proposed algorithm can reduce the number of erase operations by utilizing the sector-level mapping table when writing data at flash memory. Sector-level mapping technique reduces flash memory access time and extendsthe life time of the flash memory. In the algorithm, wear-leveling is implemented by selecting victim blocks having the minimal number of erase operations, when empty spaces for write are not available. To evaluate the performance of the proposed FTL algorithm, experiments were performed on several applications, such as MP3 players, MPEG players, web browsers and document editors. The proposed algorithm reduces the number of erase operations by 72.4% and 61.9%, when compared with well-known BAST and FAST algorithms, respectively.

• KIISE Transactions on Computing Practices
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• v.22 no.10
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• pp.497-503
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• 2016

Emerging next-generation storage technologies such as non-volatile memory will help eliminate almost all of the storage latency that has plagued previous storage devices. In conventional storage systems, the latency of slow storage devices dominates access latency; hence, software efficiency is not critical. With low-latency storage, software costs can quickly dominate memory latency. Hence, researchers have proposed the memory mapped file I/O to avoid the software overhead. Mapping a file into the user memory space enables users to access the file directly. Therefore, it is possible to avoid the complicated I/O stack. This minimizes the number of user/kernel mode switchings. In addition, there is no data copy between kernel and user areas. Despite of the benefits in the memory mapped file I/O, its overhead still needs to be addressed, as the existing mechanism for the memory mapped file I/O is designed for slow block devices. In this paper, we identify the overheads of the memory mapped file I/O via experiments.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10c
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• pp.9-11
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• 1999

3차원 그래픽 랜더링 파이프라인(3D Graphics Rendering Pipeline)은 크게 지오메트리 프로세싱(Geometry Processing)과 레스터라이제이션(Rasterization)으로 구성되어 있다. 본 논문에서는 래스터라이저와 프레임버퍼사이의 대역폭으로 인한 병목점을 분석하고, 그 한계를 극복해 낼 수 있도록 프로세서 메모리 집적구조를 이용하여 랜더링 시스템을 설계, 성능 분석한다. 프레임버퍼의 집적으로 인한 메모리 대역폭을 이용하기 위해, 각 픽셀 처리에 필요한 로직을 포함하는 SIMD 타입의 픽셀 처리 프로세서가 메모리 어레이와 밀결합(tightly coupled)된다. 제안하는 구조는 래스터라이저 로직과 프레임 버퍼가 단일 칩으로 구성되었고, 텍스쳐 매핑, 범프 매핑, 안티알리아싱, 깊이 버퍼를 지원하며 초당 5백만 이상의 삼각형을 처리할 수 있는 고성능 랜더링 시스템이다.

• Journal of the Korea Society of Computer and Information
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• v.20 no.5
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• pp.1-12
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• 2015

NAND flash memory has being used for storage systems widely, because it has good features which are low-price, low-power and fast access speed. However, NAND flash memory has an in-place update problem, and therefore it needs FTL(flash translation layer) to run for applications based on hard disk storage. The FTL includes complex functions, such as address mapping, garbage collection, wear leveling and so on. Futhermore, implementation of the FTL on low-power embedded systems is difficult due to its memory requirements and operation overhead. Accordingly, many index data structures for NAND flash memory have being studied for the embedded systems. Overall performances of the index data structures are enhanced by a decreasing of page write counts, whereas it has increased page read counts, as a side effect. Therefore, we propose an index management method using a page mapping log table in $B^+$-Tree based on NAND flash memory to decrease page write counts and not to increase page read counts. The page mapping log table registers page address information of changed index node and then it is exploited when retrieving records. In our experiment, the proposed method reduces the page read counts about 61% at maximum and the page write counts about 31% at maximum, compared to the related studies of index data structures.

• Proceedings of the Korea Information Processing Society Conference
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• 2003.11a
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• pp.119-122
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• 2003

본 논문에서는 분산메모리 멀티프로세서 시스템에서 태스크와 프로세서 노드간의 매핑에 관한 최적화 문제를 메타휴리스틱스(metatheuristics)의 장점을 효과적으로 결합한 새로운 방안을 소개한다. 태스크-프로세서 할당에 있어 부하균형을 고려한 MFA-GA 하이브리드 알고리즘을 제안하고 기존의 할당 방안들과 성능실험을 통해 비교 분석한다. 우리의 합성 휴리스틱을 이용하면 각 방법을 단독으로 사용하는 것 보다 매핑 품질과 수행시간 면에서 개선된 성능결과를 얻을 수 있음을 보여주었다.

• Proceedings of the Korean Society of Computer Information Conference
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• 2019.01a
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• pp.415-418
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• 2019

최근 사용자 대화형(user-interactive) 응용들은 OS에게 많은 양의 메모리를 빈번하게 요구한다는 특징을 보인다. 응용의 메모리 할당 요청이 발생하면 OS는 할당할 페이지의 초기화 작업을 필수적으로 수행하는데, 빈번하게 발생하는 페이지 초기화 작업이 응용의 성능을 저하시키고 있다. 기존 리눅스 기반 시스템은 페이지 초기화 지연을 단축하기 위해 CPU의 캐시에 매핑되어 있어서 초기 값을 빠르게 쓸 수 있는 페이지인 캐시-핫(cache-hot) 페이지를 우선적으로 할당한다. 하지만 기존 리눅스는 각 코어별로 캐시-핫 페이지를 인식하고 관리하며, 다른 코어가 관리하는 캐시-핫 페이지에는 접근할 수 없다. 이러한 정책 때문에 다른 코어가 공유 캐시(shared cache)에 매핑된 캐시-핫 페이지를 관리하고 있더라도, 이를 할당받지 못하고 캐시-콜드(cache-cold) 페이지를 할당받는 경우가 발생한다. 본 논문에서는 공유 캐시에 매핑된 것으로 추정되는 캐시-핫 페이지를 별도로 인식하고 공유 캐시에 매핑된 것으로 추정되는 캐시-핫 페이지를 모든 코어가 활용할 수 있게 하여, 응용이 캐시-핫 페이지를 할당받을 확률을 기존 기법보다 높이는 향상된 캐시-핫 페이지 할당 기법을 제안한다. 제안된 기법은 페이지 할당 요청이 발생하면 먼저 각 코어의 사유 캐시에 매핑된 것으로 추정되는 캐시-핫 페이지를 우선적으로 할당하고, 할당에 실패하면 공유 캐시에 매핑된 것으로 추정되는 캐시-핫 페이지를 할당한다. 이를 통해 캐시-핫 페이지를 할당받을 확률을 기존 기법보다 높이고, 결과적으로 평균 페이지 초기화 지연을 단축한다. 제안된 기법을 리눅스 커널 4.18.10버전 기반 환경에서 구현하여 실험한 결과, 평균 페이지 초기화 지연이 기존 리눅스 시스템과 비교하여 약 7% 단축되었다.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.5_6
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• pp.213-222
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• 2003

Most existing algorithms adopt the forward mapping method that is based on vector representation. Problem of existing algorithms Is the exponential increase of memory usage with number of layers. This degrades the accuracy of the boundary pattern representation. Our method uses bitmap representation and does not require any additional post-processing for conversion of vector-form results to bitmap-form. A new and efficient algorithm is presented in this paper for the generation of hyperbolic patterns by means of backward mapping methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.7B
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• pp.818-826
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• 2011

This paper proposes a novel FTL (Flash Translation Layer) algorithm employing sector-level mapping technique based on locality to reduce the number of erase operations in flash memory accesses. Sector-level mapping technique shows higher performance than other mapping techniques, even if it requires a large mapping table. The proposed algorithm reduces the size of mapping table by employing dynamic table update, processes sequential writes by exploiting sequential locality and extracts hot sector in random writes. Experimental results show that the number of erase operations has been reduced by 75.4%, 65.8%, and 10.3% respectively when compared with well-known BAST, FAST and sector mapping algorithms.

• Journal of the Korea Computer Graphics Society
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• v.6 no.4
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• pp.35-42
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• 2000

3D texture mapping generates highly natural visual effects in which objects appear carved from lumps of materials rather than laminated with thin sheets as in 2D texture mapping. Storing 3D texture images in a table for fast mapping computations, instead of evaluating procedures on the fly, however, has been considered impractical due to the extremely high memory requirement. Recently, a practical real-time 3D texture mapping technique was proposed in [11], where they attempt to resolve the potential texture memory problem by compressing 3D textures using a wavelet-based encoding method. In this paper, we consider two other encoding schemes that could also be applied to the compression-based 3D texture mapping. In particular, we extend the vector quantization and FXT1 for 3D texture compression, and compare their performance with the wavelet-based encoding scheme.