• Journal of KIISE:Computer Systems and Theory
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• v.28 no.9
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• pp.434-441
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• 2001

The concept of network memory was introduced for the efficient exploitation of main memory in a cluster. Network memory can be used to speed up applications that frequently access large amount of disk data. In this paper, we present a memory a management algorithm that does not require prior knowledge of access patterns and that is practical to implement under the web server cluster, In addition, our scheme has a good user response time for various access distributions of web documents. Through a detailed simulation, we evaluate the performance of our memory managment algorithms.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.11a
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• pp.755-758
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• 2007

플래시 메모리는 휴대폰, MP3 플레이어, 개인휴대정보단말기(PDA), 휴대용 멀티미디어 플레이어(PMP), 디지털 카메라 및 캠코더와 같은 이동성이 강한 소형기기에서 가장 많이 사용되는 저장 매체이다. 최근 대용량의 값싼 플래시 메모리가 등장하면서 랩톱이나 데스크톱과 같은 일반적인 컴퓨팅 환경을 지닌 기기들에서도 그 사용이 확대되고 있는 추세이다. 플래시 메모리가 보다 범용적인 저장 장치로 사용되기 위해서는 일반 컴퓨팅 환경에서의 복잡한 작업 부하에서도 우수한 성능을 제공할 수 있는 플래시 변환 계층(Flash Translation Layer)이 반드시 필요하다. 아쉽게도 현재까지 연구된 FTL 기법들은 소형기기의 단순한 작업 부하에 알맞도록 설계되어 있으며, 일반 컴퓨팅 환경과 같이 복잡한 작업 부하를 지닌 환경에서는 우수한 성능을 제공하지 못한다는 단점을 가지고 있다. 본 논문에서는 일반 컴퓨팅 환경의 복잡한 작업 부하에 대해서도 우수한 가비지 수집 성능을 제공하는 새로운 로그 블록 교체 기법을 제안하였다. 실험을 통한 평가 결과, 제안한 기법은 기존 기법 대비 평균 35% 정도의 가비지 수집 부하를 감소시키는 것으로 나타났다.

• Proceedings of the Korea Information Processing Society Conference
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• 2008.11a
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• pp.806-809
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• 2008

온칩(on-chip) 캐쉬는 외부 메모리로의 접근을 감소시키는 중요한 역할을 한다. 본 연구에서는 내장형 시스템에 맞추어 설계된 2-레벨 캐쉬 메모리 구조를 제안하고자 한다. 레벨1(L1) 캐쉬의 구성으로 작은 크기, 직접사상(direct-mapped) 그리고 바로쓰기(write-through)를 채용한다. 대조적으로 레벨2(L2) 캐쉬는 일반적인 캐쉬 크기와 집합연관(Set-associativity) 그리고 나중쓰기(write-back) 정책을 채용한다. 결과적으로 L1캐쉬는 한 사이클 이내에 접근될 수 있고 L2캐쉬는 전체 캐쉬의 미스율(global miss rate)을 낮추는데 효과적이다. 두 캐쉬 계층간 바로쓰기(write-thorough) 정책에서 오는 빈번한 L2 캐쉬 접근으로 인한 에너지 소비를 줄이기 위해 본 연구에서는 One-way 접근 기법을 제안하였다. 본 연구에서 제안한 2-레벨 캐쉬 메모리 구조는 평균적으로 26%의 성능향상과 43%의 에너지 소비 그리고 77%의 에너지-지연 곱에서 이득을 보여주었다.

• The KIPS Transactions:PartA
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• v.12A no.3 s.93
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• pp.215-222
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• 2005

The efficient utilization of cache memories is a key factor in achieving high performance for computing large signal transforms. Nonunit stride access in computation of large DFTs causes cache conflict misses, thereby resulting in poor cache performance. It leads to a severe degradation in overall performance. In this paper, we propose a dynamic data layout approach considering the memory hierarchy system. In our approach, data reorganization is performed between computation stages to reduce the number of cache misses. Also, we develop an efficient search algorithm to determine the optimal tree with the minimum execution time among possible factorization trees considering the size of DFTs and the data access stride. Our approach is applied to compute the fast Fourier Transform (FFT). Experiments were performed on Pentium 4, $Athlon^{TM}$ 64, Alpha 21264, UtraSPARC III. Experiment results show that our FFT achieve performance improvement of up to 3.37 times better than the previous FFT packages.

• Journal of the Korea Society of Computer and Information
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• v.20 no.4
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• pp.1-10
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• 2015

NAND flash systems require deletion operation and do not support in-place update, so the storage systems should use Flash Translation Layer (FTL). However, there are a lot of memory consumptions using mapping table in the FTL, so recently, many studies have been proposed to resolve mapping table overhead. These studies try to solve update propagation problem in the nand flash system which does not use mapping table. In this paper, we present a novel index structure, called CL-Tree(Cache List Tree), to solve the update propagation problem. The proposed index structure reduces write operations which occur for an update propagation, and it has a good performance for search operation because it uses multi-list structure. In experimental evaluation, we show that our scheme yields about 173% and 179% improvement in insertion speed and search speed, respectively, compared to traditional B+tree and other works.

• Journal of Digital Contents Society
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• v.14 no.2
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• pp.215-222
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• 2013

NAND flash memory-based Solid State Drives (SSD) have lots of merits compared to traditional hard disk drives (HDD). However, random write in SSD is still far slower than sequential read/write and random read. There are two independent approaches to resolve this problem: 1) using part of the flash memory blocks as log blocks, and 2) using internal write buffer (DRAM or Non-Volatile RAM) in SSD. While log blocks are managed by the Flash Translation Layer (FTL), write buffer management has been treated separately from FTL. Write buffer management schemes did not use the exact status of log blocks and log block management schemes in FTL did not consider the behavior of write buffer management scheme. In this paper, we first show that log blocks and write buffer have a tight relationship to each other, which necessitates integrated management of both of them. Since log blocks also can be viewed as another type of write buffer, we can manage both of them as an integrated write buffer. Then we provide three design criteria for the integrated write buffer management scheme which can be very useful to SSD firmware designers.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.6
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• pp.463-475
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• 2009

Flash memory is suitable for real time systems because of its consistent performance for random access, low power consumption and shock resistance. However, flash memory needs blocking time to perform a garbage collection to reclaim invalidated pages. Moreover, the worst-case garbage collection time is significantly longer than the best-case garbage collection time. In this paper, we propose a FTL (Flash Translation Layer) mapping scheme called KAST (K-Associative Sector Translation). In the KAST scheme, user can control the maximum association of the log block to limit the worst-case garbage collection time. Performance evaluation using simulation shows that not only KAST completes the garbage collection within the specified time but also provides about 10~15% better average performance than existing FTL schemes.

• The Journal of the Korea Contents Association
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• v.13 no.9
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• pp.28-38
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• 2013

During the past decades, the B+-tree has been most widely used as an index file structure for disk-resident databases. For the disk based B+-tree, a node update can be cheaply performed just by modifying its associated disk page in place. However, in case that the B+-tree is stored on flash memory, the traditional algorithms of the B+-tree come to be useless due to the prohibitive cost of in-place updates on flash memory. For this reason, the earlier schemes for flash memory B+-trees usually take an approach that saves B+-tree changes from real-time updates into extra temporary storage. Although that approach can easily prevent frequent in-place updates in the B+-tree, it can suffer from a waste of storage space and prolonged search times. Particularly, it is not allowable to process range searches on the leaf node level. To resolve such problems, we devise a new scheme in which the leaf nodes and their parent node are stored together in a single flash block, called the p-node block.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.2
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• pp.77-88
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• 2009

According to the size of NAND flash memory as the storage system of mobile device becomes large, the performance of address translation and life cycle management in FTL (Flash Translation Layer) to interact with file system becomes very important. In this paper, we propose the continuity counters, which represent the number of continuous physical blocks whose logical addresses are consecutive, to reduce the number of address translation. Furthermore we propose the prefetching method which preloads frequently accessed pages into main memory to enhance I/O performance of flash memory. Besides, we use the 2-bit write prediction and asynchronous writing method to predict addresses repeatedly referenced from host and prevent from writing overhead. The experiments show that the proposed method improves the I/O performance and extends the life cycle of flash memory. As a result, proposed CFTL (Clustered Flash Translation Layer)'s performance of address translation is faster 20% than conventional FTLs. Furthermore, CFTL is reduced about 50% writing time than that of conventional FTLs.

• The KIPS Transactions:PartA
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• v.15A no.6
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• pp.335-344
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• 2008

We propose an adaptive garbage collection technique for hybrid flash memory which has both SLC and MLC. Since SLC area is fast and MLC area has low cost, the proposed scheme utilizes the SLC area as log buffer and the MLC area as data block. Considering the high write cost of MLC flash, the garbage collection for the SLC log buffer moves a page into the MLC data block only when the page is cold or the page migration invokes a small cost. The other pages are moved within the SLC log buffer. Also it adjusts the parameter values which determine the operation of garbage collection adaptively considering I/O pattern. From the experiments, we can know that the proposed scheme provides better performance compared with the previous flash management schemes for the hybrid flash and finds the parameter values of garbage collection close to the optimal values.