• Journal of the Korea Institute of Information Security & Cryptology
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• v.29 no.2
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• pp.431-438
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• 2019

Fileless malware uses memory injection attacks to hide traces of payloads to perform malicious works. During the memory injection attack, an attack named "process hollowing" is a method of creating paused benign process like system processes. And then injecting a malicious payload into the benign process allows malicious behavior by pretending to be a normal process. In this paper, we propose a method to detect the memory injection regardless of whether or not the malicious action is actually performed when a process hollowing attack occurs. The replication process having same execution condition as the process of suspending the memory injection is executed, the data set belonging to each process virtual memory area is compared using the fuzzy hash, and the similarity is calculated.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.122-130
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• 2013

The demand and the supply are increasing sharply in accordance with the growth of the Memory Semiconductor Industry. The Flash Memory above all is being utilized substantially in the Industry of smart phone, the tablet PC and the System on Chip (SoC). The Flash Memory is divided into the NOR-type Flash Memory and the NAND-type Flash Memory. A lot of study such as the Built-In Self Test (BIST), the Built-In Self Repair (BISR) and the Built-In Redundancy Analysis (BIRA), etc. has been progressed in the NOR-type fash Memory, the study for the Built-In Self Test of the NAND-type Flash Memory has not been progressed. At present, the pattern test of the NAND-type Flash Memory is being carried out using the outside test equipment of high price. The NAND-type Flash Memory is being depended on the outside equipment as there is no Built-In Self Test since the erasure of block unit, the reading and writing of page unit are possible in the NAND-type Flash Memory. The Built-In Self Test equipped with 2 kinds of finite state machine based structure is proposed, so as to carry out the pattern test without the outside pattern test equipment from the NAND-type Flash Memory which carried out the test dependant on the outside pattern test equipment of high price.

• Computational Structural Engineering
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• v.4 no.2
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• pp.103-110
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• 1991

To solve the large problems with limited core memory of computer, a disk management scheme called virtual memory database has been developed. Utilizing this technique along with memory moving scheme, an efficient in-and out-of-core column solver for the sparse symmetric matrix commonly arising in the finite element analysis is developed. Compared with other methods the algorithm is simple, therefore the coding and computational efficiencies are greatly enhanced. Analysis example shows that the proposed method efficiently solve the large structural problem on the small-memory micro-computer.

• Journal of KIISE
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• v.43 no.5
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• pp.524-530
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• 2016

The desire to access data faster and the growth of next-generation memories such as non-volatile memories, contribute to the development of research on memory file systems. It is recommended that memory mapped file I/O, which has less overhead than read-write I/O, is utilized in a high-performance memory file system. Memory mapped file I/O, however, brings a page table overhead, which becomes one of the big overheads that needs to be resolved in the entire file I/O performance. We find that same overheads occur unnecessarily, because a page table of a file is removed whenever a file is opened after being closed. To remove the duplicated overhead, we propose the mapping cache, a technique that does not delete a page table of a file but saves the page table to be reused when the mapping of the file is released. We demonstrate that mapping cache improves the performance of traditional file I/O by 2.8x and web server performance by 12%.

• Journal of the Korea Society of Computer and Information
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• v.13 no.3
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• pp.57-63
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• 2008

As diverse memory cards based on NAND flash memory are getting popularity with consumer electronics such as digital camera, camcorder and MP3 player the compatibility problems between a newly developed memory card and existent host systems have become a main obstacle to time-to-market delivery of product. The common practice for memory card compatibility test is to use a real host system as a test bed. As an improved solution, an FPGA-based prototyping board can be used for emulating host systems. However, the above approaches require a long set-up time and have limitations in representing various host and device systems. In this paper, we propose a co-validation environment for compatibility test between memory card and host system using formal modeling based on Esterel language and co-simulation methodology. Finally, we demonstrate the usefulness of the proposed environment with a case study of real memory card development.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.4
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• pp.35-41
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• 2008

When memory devices are exposed to a space environment. they suffer various effects such as SEU(Single Event Upset). For these reasons, memory systems for space applications are generally equipped with error detection and correction(EDAC) logics against SEUs. In this paper, the error detection and correction strategy in the Mass Memory Unit(MMU) of the STSAT-3 is discussed. The probability equation of un-recoverable SEUs in the mass memory system is derived when the whole memory is encoded and decoded by the RS(10,8) Reed-Solomon code. Also the probability value is analyzed for various occurrence rates of SEUs which the STSAT-3 possibly suffers. The analyzed results can be used to determine the period of scrubbing the whole memory, which is one of the important parameters in the design of the MMU.

• The KIPS Transactions:PartA
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• v.14A no.1 s.105
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• pp.39-46
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• 2007

Recently flash memory is widely accepted as a storage devise of embedded systems for portability and performance reasons. Flash memory has many distinguishing features compared to legacy magnetic disks. Especially, a file system for flash memory usually assumes the form of log-structured file system and it employs garbage collector accordingly. Since the garbage collector can greatly affect the performance of file system, it should be designed carefully considering flash memory features. In this paper, we suggest a new garbage collector for existing JFFS2 (Journaling Flash File System II) file system. By extensive performance evaluation, we show that the proposed garbage collector achieves improved performance in terms of flash memory consumption rate, increased flash memory life time, and improved wear-leveling.

• Proceedings of the Korean Society of Computer Information Conference
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• 2013.01a
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• pp.195-196
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• 2013

본 논문에서는 NVRAM(Non-volatile Random Access Memory) 주 기억장치를 위한 메모리 컨트롤러를 설계한다. NVRAM의 비 휘발성과 낮은 정적 에너지 소모의 장점을 활용하는 한편, 상대적으로 느린 읽기/쓰기 속도 및 큰 쓰기 전력 소모를 개선하기 위해 새로운 캐시 구조를 제안한다. FPGA를 활용하여 Block RAM 128KB 1차 캐시, 16KB 2차 캐시 및 캐시 컨트롤러를 포함하는 메모리 컨트롤러를 구현하였고 NVRAM은 FeRAM를 사용하였다.

• Journal of Broadcast Engineering
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• v.16 no.2
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• pp.339-349
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• 2011

IBDI (Internal Bit Depth Increase) is able to significantly improve the coding efficiency of high definition video compression by increasing the bit depth (or precision) of internal arithmetic operation. However the scheme also increases required internal memory for storing decoded reference frames and this can be significant for higher definition of video contents. So, the reference frame memory compression method is proposed to reduce such internal memory requirement. The reference memory compression is performed on 4x4 block called the processing unit to compress the decoded image using the correlation of nearby pixel values. This method has successively reduced the reference frame memory while preserving the coding efficiency of IBDI. However, additional information of each processing unit has to be stored also in internal memory, the amount of additional information could be a limitation of the effectiveness of memory compression scheme. To relax this limitation of previous memory compression scheme, we propose a selective merging-based reference frame memory compression algorithm, dramatically reducing the amount of additional information. Simulation results show that the proposed algorithm provides much smaller overhead than that of the previous algorithm while keeping the coding efficiency of IBDI.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.55-62
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• 2012

The development of memory design and process technology enabled the production of high density memory. As the weight of embedded memory within aggregate Systems-On-Chips(SoC) gradually increases to 80-90% of the number of total transistors, the importance of testing embedded dual-port memories in SoC increases. This paper proposes a new micro-code based programmable memory Built-In Self-Test(PMBIST) architecture for dual-port memories that support test various test algorithms. In addition, various test algorithms including March based algorithms and dual-port memory test algorithms are efficiently programmed through the proposed algorithm instruction set. This PMBIST has an optimized hardware overhead, since test algorithm can be implemented with the minimum bits by the optimized algorithm instructions.