• Title/Summary/Keyword: 멀티 코어 프로세서

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Collaborative Streamlined On-Chip Software Architecture on Heterogenous Multi-Cores for Low-Power Reactive Control in Automotive Embedded Processors (차량용 임베디드 프로세서에서 저전력 반응적 제어를 위한 이기종 멀티코어 협력적 스트리밍 온-칩 소프트웨어 구조)

  • Jisu, Kwon;Daejin, Park
    • IEMEK Journal of Embedded Systems and Applications
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    • v.17 no.6
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    • pp.375-382
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    • 2022
  • This paper proposes a multi-core cooperative computing structure considering the heterogeneous features of automotive embedded on-chip software. The automotive embedded software has the heterogeneous execution flow properties for various hardware drives. Software developed with a homogeneous execution flow without considering these properties will incur inefficient overhead due to core latency and load. The proposed method was evaluated on an target board on which a automotive MCU (micro-controller unit) with built-in multi-cores was mounted. We demonstrate an overhead reduction when software including common embedded system tasks, such as ADC sampling, DSP operations, and communication interfaces, are implemented in a heterogeneous execution flow. When we used the proposed method, embedded software was able to take advantage of idle states that occur between heterogeneous tasks to make efficient use of the resources on the board. As a result of the experiments, the power consumption of the board decreased by 42.11% compared to the baseline. Furthermore, the time required to process the same amount of sampling data was reduced by 27.09%. Experimental results validate the efficiency of the proposed multi-core cooperative heterogeneous embedded software execution technique.

Synchronized Sampling Structure applied HW/SW platform for LAN-based Digital Substation Protection (LAN 기반 디지털 변전소 보호를 위한 동기 샘플링 구조적용 HW/SW 플랫폼 기술)

  • Son, Kyou Jung;Nam, Kyung-Deok;An, Gi Sung;Chang, Tae Gyu
    • Journal of IKEEE
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    • v.24 no.1
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    • pp.178-185
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    • 2020
  • This paper proposes precise time synchronization-based synchronized sampling structure applied HW/SW platform for LAN-based protection of future digital substations. The integrated software of the proposed platform includes IEC 61850 protocol, IEEE 1588 precision time protocol and synchronized sampling structure. The proposed platform expected to provide a basis of an application of future distributed sensing data-based protection and control methods by providing synchronized measurement among IEDs. The implementation of the proposed HW/SW platform technique was performed using TMDXIDK572 multi-core/multi-processor evaluation module and its time synchronization performance and synchronized sampling function were confirmed through the performance tests.

Measuring ultrasonic TOF using Zynq baremetal Multiprocessing (Zynq 기반 baremetal 멀티프로세싱에 의한 초음파 TOF 측정)

  • Kang, Moon ho
    • Journal of the Institute of Electronics and Information Engineers
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    • v.54 no.6
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    • pp.93-99
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    • 2017
  • In this research the TOF (time of flight) of ultrasonic signal is measured using Xilinx's Zynq SoC (system on chip). The TOF is calculated from the difference between periods during which RF (radio frequency) and ultrasonic signals come across a distance, and then travelling distance is obtained by multiplying the TOF by the ultrasonic speed in the air. For this purpose, a ultrasonic pulse is generated from a Zynq's internal ADC, a FIR (finite impulse response) filter, and a Kalman filter. And a RF reference pulse is generated from a RF interface. Based on baremetal multiprocessing, the Kalman filter and the RF interface are c-programmed on Zynq's dual processor cores, with other components fabricated on Zynq's FPGA. With this HW/SW co-design, both lower resource utilization and much smaller designing period were obtained than the HW design. As a design tool, Vivado IDE(integrated design environment) is used to design the whole signal processing system in hierarchical block diagrams.

Development of RTEMS SMP Platform Based on XtratuM Virtualization Environment for Satellite Flight Software (위성비행소프트웨어를 위한 XtratuM 가상화 기반의 RTEMS SMP 플랫폼)

  • Kim, Sun-wook;Choi, Jong-Wook;Jeong, Jae-Yeop;Yoo, Bum-Soo
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.48 no.6
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    • pp.467-478
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    • 2020
  • Hypervisor virtualize hardware resources to utilize them more effectively. At the same time, hypervisor's characteristics of time and space partitioning improves reliability of flight software by reducing a complexity of the flight software. Korea Aerospace Research Institute chooses one of hypervisors for space, XtratuM, and examine its applicability to the flight software. XtratuM has strong points in performance improvement with high reliability. However, it does not support SMP. Therefore, it has limitation in using it with high performance applications including satellite altitude orbit control systems. This paper proposes RTEMS XM-SMP to support SMP with RTEMS, one of real time operating systems for space. Several components are added as hypercalls, and initialization processes are modified to use several processors with inter processors communication routines. In addition, all components related to processors are updated including context switch and interrupts. The effectiveness of the developed RTEMS XM-SMP is demonstrated with a GR740 board by executing SMP benchmark functions. Performance improvements are reviewed to check the effectiveness of SMP operations.

A Design and Implementation of Educational Mobile Robot System including Remote Control Function (원격 제어 기능을 포함한 교육용 모바일 로봇 시스템의 설계 및 구현)

  • Chung, Joong-Soo;Jung, Kwang-Wook
    • Journal of the Korea Society of Computer and Information
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    • v.20 no.4
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    • pp.33-40
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    • 2015
  • This paper presents the design and implementation of the educational remote controlled robot system including remote sensing in the embedded environment. The design of sensing information processing, software design and template design mechanism for the programming practice are introduced. LPC1769 using Cortex-M3 core as CPU, LPCXPRESSO as debugging environment, C language as firmware development language and FreeRTOS as OS are used in development environment. The control command is received via RF communication by the server and the robot system which is operated by driving the various sensors. The educational procedure is from robot demo operation program as hands-on practice and then compiling, loading of the basic robot operation program, already supplied. Thereafter the verification is checked by using the basic robot operation to allow demo operation such as hands-on-training procedure. The original protocol is designed via RF communication between server and robot system, and the satisfied performance result is presented by analyzing the robot sensing data processing.

IPC-based Dynamic SM management on GPGPU for Executing AES Algorithm

  • Son, Dong Oh;Choi, Hong Jun;Kim, Cheol Hong
    • Journal of the Korea Society of Computer and Information
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    • v.25 no.2
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    • pp.11-19
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    • 2020
  • Modern GPU can execute general purpose computation on the graphic processing unit, and provide high performance by exploiting many core on GPU. To run AES algorithm efficiently, parallel computational resources are required. However, computational resource of CPU architecture are not enough to cryptographic algorithm such as AES whereas GPU architecture has mass parallel computation resources. Therefore, this paper reduce the time to execute AES by employing parallel computational resource on GPGPU. Unfortunately, AES cannot utilize computational resource on GPGPU since it isn't suitable to GPGPU architecture. In this paper, IPC based dynamic SM management technique are proposed to efficiently execute AES on GPGPU. IPC based dynamic SM management can increase and decrease the number of active SMs by using IPC in run-time. According to simulation results, proposed technique improve the performance by increasing resource utilization compared to baseline GPGPU architecture. The results show that AES improve the performance by 41.2% on average.

Design and Implementation of Initial OpenSHMEM Based on PCI Express (PCI Express 기반 OpenSHMEM 초기 설계 및 구현)

  • Joo, Young-Woong;Choi, Min
    • KIPS Transactions on Computer and Communication Systems
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    • v.6 no.3
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    • pp.105-112
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    • 2017
  • PCI Express is a bus technology that connects the processor and the peripheral I/O devices that widely used as an industry standard because it has the characteristics of high-speed, low power. In addition, PCI Express is system interconnect technology such as Ethernet and Infiniband used in high-performance computing and computer cluster. PGAS(partitioned global address space) programming model is often used to implement the one-sided RDMA(remote direct memory access) from multi-host systems, such as computer clusters. In this paper, we design and implement a OpenSHMEM API based on PCI Express maintaining the existing features of OpenSHMEM to implement RDMA based on PCI Express. We perform experiment with implemented OpenSHMEM API through a matrix multiplication example from system which PCs connected with NTB(non-transparent bridge) technology of PCI Express. The PCI Express interconnection network is currently very expensive and is not yet widely available to the general public. Nevertheless, we actually implemented and evaluated a PCI Express based interconnection network on the RDK evaluation board. In addition, we have implemented the OpenSHMEM software stack, which is of great interest recently.