• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.6
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• pp.714-721
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• 2020

DNN is expanding its use in embedded systems such as robots and autonomous vehicles. For high recognition accuracy, computational complexity is greatly increased, and multiple DNNs are running aperiodically. Therefore, the ability processing multiple DNNs in embedded environments is a crucial issue. Accordingly, multicore based platforms are being released. However, most DNN models are operated in a batch process, and when multiple DNNs are operated in multicore together, the execution time deviation between each DNN may be large and the end-to-end execution time of the whole DNNs could be long depending on how they are allocated to the cores. In this paper, we solve these problems by providing a framework that decompose each DNN into individual layers and then distribute to multicores through a global queue. As a result of the experiment, the total DNN execution time was reduced by 31%, and when operating multiple identical DNNs, the deviation in execution time was reduced by up to 95.1%.

• The Journal of the Korea Contents Association
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• v.18 no.4
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• pp.178-185
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• 2018

Recently, demands for computer systems with multicore CPUs and high-performance flash-based storage devices (i.e., flash SSD) have rapidly grown in cloud computing, surer-computing, and enterprise storage/database systems. Journaling file systems running on high-performance systems do not exploit the full I/O bandwidth of high-performance SSDs. In this article, we evaluate and analyze the performance of the Linux EXT4 file system with high-performance SSDs and multicore CPUs. The system used in this study has 72 cores and Intel NVMe SSD, and the flash SSD has performance up to 2800/1900 MB/s for sequential read/write operations. Our experimental results show that checkpointing in the EXT4 file system is a major overhead. Furthermore, we optimize the checkpointing procedure and our optimized EXT4 file system shows up to 92% better performance than the original EXT4 file system.

• Journal of IKEEE
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• v.17 no.4
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• pp.564-569
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• 2013

The current embedded devices are growing rapidly in the multi-core, and these demand fast boot time. But method of previous boot uses core only one. The method includes parallel techniques and modification of CPU Frequency policy. Parallel methods, after analyzing the Android boot process with analysis tool, applied to location where a lot of CPU operation. CPU Frequency policy is modified for high performance of core. The proposed method was applied to S5PV310 dual core and Exynos4412 quad core embedded system. As a result of the experiment, we found that the proposed method makes boot time fast about 20.71% and 31.34% in dual core and quad core environment as compared with the previous method.

• Proceedings of the Korean Information Science Society Conference
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• 2010.06b
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• pp.425-430
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• 2010

항공기 내에서 단일코어 기반의 임무컴퓨터를 포함하는 연합형 항공전자 모델은 항공기의 임무 요구도 증대와 전장 환경의 변화에 따라 기내 데이터 양이 급격히 증가하여 비행 운용 프로그램(OFP)의 실시간성 및 처리성능에 한계를 보인다. 또한 분산된 임무컴퓨터의 공간점유와 무게 및 높은 전력소비가 발생하므로, 본 연구에서는 실시간 운영체제 모듈을 적용한 멀티코어 기반의 통합 모듈형 시스템(IMA) 플랫폼을 제시하여 비용과 체적을 감소시킨 개발 환경을 제공한다.

• Journal of Aerospace System Engineering
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• v.13 no.5
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• pp.1-8
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• 2019

Recently, avionics has been migrating from a federated architecture to an integrated modular architecture based on a multi-core to reduce the number of systems, weight, power consumption, and platform redundancy. The volume of data which must bo provided to the pilot through the display device has increased, because an integrated single device performs multiple functions. For this reason, the volume of data processed by the graphic processor within a fixed operation period has increased. In this paper, we provide a multi-core-based rendering engine in to perform more graphics processing within a fixed operation period. We assume the proposed method uses a multi-core-based partitioning operating system using the AMP (Asymmetric Multi-Processing) architecture.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.8
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• pp.863-867
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• 2010

Multi-core processors are becoming increasingly popular. As they are widely adopted in embedded systems as well as desktop PC's, many multimedia applications are being parallelized on multi-core platforms. However, it is difficult to parallelize applications with inherent data dependencies such as encryption algorithms for multimedia data. In order to overcome this limit, we propose a technique to overlap computation and communication using an otherwise idle core in this paper. In particular, we interpret the problem of multimedia computation and communication as a pipeline design problem at the application program level, and derive an optimal number of stages in the pipeline.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06a
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• pp.4-6
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• 2012

최근 멀티코어 CPU가 장착된 시스템들이 출시되면서 많은 병렬처리 기법들이 제안되고 있다. 본 논문에서는 데이터 종속성이 없는 모듈과 종속성이 있는 모듈이 순차적으로 구성된 응용에서 각 코어에 부하를 효과적으로 분산시키는 방법을 제안한다. 즉, 데이터 종속성이 없는 모듈을 각 코어에 대칭적으로 분산시키는 통상적인 방법 대신, 비대칭적으로 부하를 분산시킴으로써 암달의 법칙에서 계산된 성능 상한치를 뛰어넘는 성능 개선을 얻을 수 있음을 보인다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.2
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• pp.251-256
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• 2017

Recently, multicore processor system is widely adopted not only in general purpose computers but also in embedded systems and mobile devices in order to improve performance. Since the power dissipation issue of multicore processor system is very significant, it must be estimated accurately in the early design stage. In this paper, a fast power analysis tool for a high performance multicore processor based on the trace-driven simulator has been developed. To achieve it, the power dissipation of each hardware unit per core are added. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed to estimate the average power dissipation per instruction.

• Journal of the Korea Society for Simulation
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• v.27 no.3
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• pp.1-11
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• 2018

Discrete event system specification (DEVS) has been used in many simulations including hybrid systems featuring both discrete and continuous behavior that require a lot of time to get results. Therefore, in this study, we proposed the acceleration of a DEVS-based hybrid system simulation using multi-cores and GPUs tightly coupled computing. We analyzed the proposed heterogeneous computing of the simulation in terms of the configuration of the target device, changing simulation parameters, and power consumption for efficient simulation. The result revealed that the proposed architecture offers an advantage for high-performance simulation in terms of execution time, although more power consumption is required. With these results, we discovered that our approach is applicable in hybrid system simulation, and we demonstrated the possibility of optimized hardware distribution in terms of power consumption versus execution time via experiments in the proposed architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.6
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• pp.521-530
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• 2013

This paper proposes a task parallelism system (BioMP) to improve applications' execution time of multicore based mobile device. When application developers append the functions of parallel specification into the existing software, our proposed system supports the parallel processing of threads as well as a compatibility. BioMP improves the software in order that an existing large-scale source can recognize the multicore architecture. From our experiment, our idea improved the execution time of application until about 64% against the existing system in multicore environment based on quad core. In addition, BioMP does not require any additional modification of a mobile platform because BioMP is independent component. Consequently, when application developers release multicore-aware applications into the application store, users can immediately run without any modification of the mobile device.